drm/amd/display: Array offset used before range check

Consolidating multiple CodeQL Fixes for alerts with rule id: cpp/offset-use-before-range-check

Reviewed-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Clay King <clayking@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
index 8da97a9..8d7c59e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
@@ -280,7 +280,7 @@ void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p
                j = 0;
                /* create the final dcfclk and uclk table */
                while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
-                       if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
+                       if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
                                dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
                                dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
                        } else {

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
index e968870..b5d3fd4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
@@ -285,7 +285,7 @@ void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p
                j = 0;
                /* create the final dcfclk and uclk table */
                while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
-                       if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
+                       if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
                                dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
                                dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
                        } else {

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 7cd7bdd..18388fb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -3229,7 +3229,7 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa
                        j = 0;
                        // create the final dcfclk and uclk table
                        while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
-                               if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
+                               if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
                                        dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
                                        dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
                                } else {

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
index 8839faf..e0a1dc8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
@@ -779,7 +779,7 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p
                j = 0;
                // create the final dcfclk and uclk table
                while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
-                       if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
+                       if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
                                dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
                                dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
                        } else {

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
index 895349d..201ed86 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
@@ -2192,7 +2192,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
                j = 0;
                // create the final dcfclk and uclk table
                while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
-                       if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
+                       if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
                                dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
                                dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
                        } else {