}
        WARN_ON(pll->on);
 
+       intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
+
        DRM_DEBUG_KMS("enabling %s\n", pll->name);
        pll->enable(dev_priv, pll);
        pll->on = true;
        DRM_DEBUG_KMS("disabling %s\n", pll->name);
        pll->disable(dev_priv, pll);
        pll->on = false;
+
+       intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 }
 
 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 {
        uint32_t val;
 
+       if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
+               return false;
+
        val = I915_READ(PCH_DPLL(pll->id));
        hw_state->dpll = val;
        hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
 
                DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
                              pll->name, pll->refcount, pll->on);
+
+               if (pll->refcount)
+                       intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
        }
 
        list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 
        BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
        BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
        BIT(POWER_DOMAIN_PORT_CRT) |                    \
+       BIT(POWER_DOMAIN_PLLS) |                        \
        BIT(POWER_DOMAIN_INIT))
 #define HSW_DISPLAY_POWER_DOMAINS (                            \
        (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \