drm/amd/powerplay: enable ppfeaturemask module parameter support on Vega20

Support DPM/DS/ULV related bitmasks of ppfeaturemask module parameter.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index eb70024..d18f34d 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -97,6 +97,27 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
        if (hwmgr->smu_version < 0x282100)
                data->registry_data.disallowed_features |= FEATURE_ECC_MASK;
 
+       if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK))
+               data->registry_data.disallowed_features |= FEATURE_DPM_LINK_MASK;
+
+       if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK))
+               data->registry_data.disallowed_features |= FEATURE_DPM_GFXCLK_MASK;
+
+       if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK))
+               data->registry_data.disallowed_features |= FEATURE_DPM_SOCCLK_MASK;
+
+       if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK))
+               data->registry_data.disallowed_features |= FEATURE_DPM_UCLK_MASK;
+
+       if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK))
+               data->registry_data.disallowed_features |= FEATURE_DPM_DCEFCLK_MASK;
+
+       if (!(hwmgr->feature_mask & PP_ULV_MASK))
+               data->registry_data.disallowed_features |= FEATURE_ULV_MASK;
+
+       if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK))
+               data->registry_data.disallowed_features |= FEATURE_DS_GFXCLK_MASK;
+
        data->registry_data.od_state_in_dc_support = 0;
        data->registry_data.thermal_support = 1;
        data->registry_data.skip_baco_hardware = 0;