iommu/vt-d: Enable write protect propagation from guest
authorJacob Pan <jacob.jun.pan@linux.intel.com>
Tue, 2 Mar 2021 10:13:58 +0000 (02:13 -0800)
committerJoerg Roedel <jroedel@suse.de>
Thu, 18 Mar 2021 10:42:46 +0000 (11:42 +0100)
Write protect bit, when set, inhibits supervisor writes to the read-only
pages. In guest supervisor shared virtual addressing (SVA), write-protect
should be honored upon guest bind supervisor PASID request.

This patch extends the VT-d portion of the IOMMU UAPI to include WP bit.
WPE bit of the  supervisor PASID entry will be set to match CPU CR0.WP bit.

Signed-off-by: Sanjay Kumar <sanjay.k.kumar@intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/1614680040-1989-3-git-send-email-jacob.jun.pan@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/intel/pasid.c
include/uapi/linux/iommu.h

index 629e3ae..0bf7e0a 100644 (file)
@@ -732,6 +732,9 @@ intel_pasid_setup_bind_data(struct intel_iommu *iommu, struct pasid_entry *pte,
                        return -EINVAL;
                }
                pasid_set_sre(pte);
+               /* Enable write protect WP if guest requested */
+               if (pasid_data->flags & IOMMU_SVA_VTD_GPASID_WPE)
+                       pasid_set_wpe(pte);
        }
 
        if (pasid_data->flags & IOMMU_SVA_VTD_GPASID_EAFE) {
index e1d9e75..59178fc 100644 (file)
@@ -288,7 +288,8 @@ struct iommu_gpasid_bind_data_vtd {
 #define IOMMU_SVA_VTD_GPASID_PWT       (1 << 3) /* page-level write through */
 #define IOMMU_SVA_VTD_GPASID_EMTE      (1 << 4) /* extended mem type enable */
 #define IOMMU_SVA_VTD_GPASID_CD                (1 << 5) /* PASID-level cache disable */
-#define IOMMU_SVA_VTD_GPASID_LAST      (1 << 6)
+#define IOMMU_SVA_VTD_GPASID_WPE       (1 << 6) /* Write protect enable */
+#define IOMMU_SVA_VTD_GPASID_LAST      (1 << 7)
        __u64 flags;
        __u32 pat;
        __u32 emt;