drm/msm/dpu: access CSC/CSC10 registers directly

Stop using _sspp_subblk_offset() to get offset of the csc_blk. Inline
this function and use ctx->cap->sblk->csc_blk.base directly.

As this was the last user, drop _sspp_subblk_offset() too.

Reviewed-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/534747/
Link: https://lore.kernel.org/r/20230429012353.2569481-4-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 4f58cdc..6b68ec5 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -136,30 +136,6 @@
 #define TS_CLK                 19200000
 
 
-static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx,
-               int s_id,
-               u32 *idx)
-{
-       int rc = 0;
-       const struct dpu_sspp_sub_blks *sblk;
-
-       if (!ctx || !ctx->cap || !ctx->cap->sblk)
-               return -EINVAL;
-
-       sblk = ctx->cap->sblk;
-
-       switch (s_id) {
-       case DPU_SSPP_CSC:
-       case DPU_SSPP_CSC_10BIT:
-               *idx = sblk->csc_blk.base;
-               break;
-       default:
-               rc = -EINVAL;
-       }
-
-       return rc;
-}
-
 static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
 {
        struct dpu_hw_sspp *ctx = pipe->sspp;
@@ -210,19 +186,16 @@ static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
 static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
                u32 mask, u8 en)
 {
-       u32 idx;
+       const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
        u32 opmode;
 
-       if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC_10BIT, &idx))
-               return;
-
-       opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx);
+       opmode = DPU_REG_READ(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE);
        if (en)
                opmode |= mask;
        else
                opmode &= ~mask;
 
-       DPU_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode);
+       DPU_REG_WRITE(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE, opmode);
 }
 
 /*
@@ -530,18 +503,20 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
 static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
                const struct dpu_csc_cfg *data)
 {
-       u32 idx;
+       u32 offset;
        bool csc10 = false;
 
-       if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC, &idx) || !data)
+       if (!ctx || !data)
                return;
 
+       offset = ctx->cap->sblk->csc_blk.base;
+
        if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) {
-               idx += CSC_10BIT_OFFSET;
+               offset += CSC_10BIT_OFFSET;
                csc10 = true;
        }
 
-       dpu_hw_csc_setup(&ctx->hw, idx, data, csc10);
+       dpu_hw_csc_setup(&ctx->hw, offset, data, csc10);
 }
 
 static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)