clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src

The branch clocks of gcc_cpuss_ahb_clk_src are marked critical
and hence these clocks vote on XO blocking the suspend.
De-register these clocks and its source as there is no rate
setting happening on them.

Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: stable@vger.kernel.org
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-5-8b3eaa5fb856@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c
index d5b75a5..31e788e 100644 (file)
--- a/drivers/clk/qcom/gcc-sc8180x.c
+++ b/drivers/clk/qcom/gcc-sc8180x.c
@@ -277,28 +277,6 @@ static const struct clk_parent_data gcc_parents_8[] = {
        { .hw = &gpll0_out_even.clkr.hw },
 };
 
-static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
-       F(19200000, P_BI_TCXO, 1, 0, 0),
-       F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
-       F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
-       { }
-};
-
-static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
-       .cmd_rcgr = 0x48014,
-       .mnd_width = 0,
-       .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
-       .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_cpuss_ahb_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
-};
-
 static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
        F(19200000, P_BI_TCXO, 1, 0, 0),
        F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
@@ -1656,25 +1634,6 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
        },
 };
 
-/* For CPUSS functionality the AHB clock needs to be left enabled */
-static struct clk_branch gcc_cpuss_ahb_clk = {
-       .halt_reg = 0x48000,
-       .halt_check = BRANCH_HALT_VOTED,
-       .clkr = {
-               .enable_reg = 0x52004,
-               .enable_mask = BIT(21),
-               .hw.init = &(struct clk_init_data){
-                       .name = "gcc_cpuss_ahb_clk",
-                       .parent_hws = (const struct clk_hw *[]){
-                                     &gcc_cpuss_ahb_clk_src.clkr.hw
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
 static struct clk_branch gcc_cpuss_rbcpr_clk = {
        .halt_reg = 0x48008,
        .halt_check = BRANCH_HALT,
@@ -3207,25 +3166,6 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
        },
 };
 
-/* For CPUSS functionality the SYS NOC clock needs to be left enabled */
-static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
-       .halt_reg = 0x4819c,
-       .halt_check = BRANCH_HALT_VOTED,
-       .clkr = {
-               .enable_reg = 0x52004,
-               .enable_mask = BIT(0),
-               .hw.init = &(struct clk_init_data){
-                       .name = "gcc_sys_noc_cpuss_ahb_clk",
-                       .parent_hws = (const struct clk_hw *[]){
-                                     &gcc_cpuss_ahb_clk_src.clkr.hw
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
 static struct clk_branch gcc_tsif_ahb_clk = {
        .halt_reg = 0x36004,
        .halt_check = BRANCH_HALT,
@@ -4341,8 +4281,6 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
        [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
        [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
        [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
-       [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
-       [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
        [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
        [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
        [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
@@ -4479,7 +4417,6 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
        [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
        [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
        [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
-       [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
        [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
        [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
        [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,