drm/i915/gsc: Only initialize GSC in tile 0
authorJosé Roberto de Souza <jose.souza@intel.com>
Mon, 21 Nov 2022 09:24:49 +0000 (11:24 +0200)
committerJosé Roberto de Souza <jose.souza@intel.com>
Tue, 22 Nov 2022 14:02:29 +0000 (06:02 -0800)
For multi-tile setups the GSC operational only on the tile 0.
Skip GSC auxiliary device creation for all other tiles
in GSC device init code.
Initialize basic GSC fields and use the same path
as HECI1 (HECI_PXP) device disable.

Cc: Tomas Winkler <tomas.winkler@intel.com>
Cc: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Acked-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221121092449.328674-1-alexander.usyskin@intel.com
drivers/gpu/drm/i915/gt/intel_gsc.c

index 976fdf2..bcc3605 100644 (file)
@@ -174,6 +174,14 @@ static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc,
        intf->irq = -1;
        intf->id = intf_id;
 
+       /*
+        * On the multi-tile setups the GSC is functional on the first tile only
+        */
+       if (gsc_to_gt(gsc)->info.id != 0) {
+               drm_dbg(&i915->drm, "Not initializing gsc for remote tiles\n");
+               return;
+       }
+
        if (intf_id == 0 && !HAS_HECI_PXP(i915))
                return;