dt-bindings: clk: emev2: Rename bindings documentation file

Rename the device tree clock bindings for Renesas EMMA Mobile EV2
from emev2-clock.txt to renesas,emev2-smu.txt.

This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/Documentation/devicetree/bindings/clock/emev2-clock.txt b/Documentation/devicetree/bindings/clock/emev2-clock.txt
deleted file mode 100644 (file)
index 268ca61..0000000
--- a/Documentation/devicetree/bindings/clock/emev2-clock.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-Device tree Clock bindings for Renesas EMMA Mobile EV2
-
-This binding uses the common clock binding.
-
-* SMU
-System Management Unit described in user's manual R19UH0037EJ1000_SMU.
-This is not a clock provider, but clocks under SMU depend on it.
-
-Required properties:
-- compatible: Should be "renesas,emev2-smu"
-- reg: Address and Size of SMU registers
-
-* SMU_CLKDIV
-Function block with an input mux and a divider, which corresponds to
-"Serial clock generator" in fig."Clock System Overview" of the manual,
-and "xxx frequency division setting register" (XXXCLKDIV) registers.
-This makes internal (neither input nor output) clock that is provided
-to input of xxxGCLK block.
-
-Required properties:
-- compatible: Should be "renesas,emev2-smu-clkdiv"
-- reg: Byte offset from SMU base and Bit position in the register
-- clocks: Parent clocks. Input clocks as described in clock-bindings.txt
-- #clock-cells: Should be <0>
-
-* SMU_GCLK
-Clock gating node shown as "Clock stop processing block" in the
-fig."Clock System Overview" of the manual.
-Registers are "xxx clock gate control register" (XXXGCLKCTRL).
-
-Required properties:
-- compatible: Should be "renesas,emev2-smu-gclk"
-- reg: Byte offset from SMU base and Bit position in the register
-- clocks: Input clock as described in clock-bindings.txt
-- #clock-cells: Should be <0>
-
-Example of provider:
-
-usia_u0_sclkdiv: usia_u0_sclkdiv {
-       compatible = "renesas,emev2-smu-clkdiv";
-       reg = <0x610 0>;
-       clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;
-       #clock-cells = <0>;
-};
-
-usia_u0_sclk: usia_u0_sclk {
-       compatible = "renesas,emev2-smu-gclk";
-       reg = <0x4a0 1>;
-       clocks = <&usia_u0_sclkdiv>;
-       #clock-cells = <0>;
-};
-
-Example of consumer:
-
-serial@e1020000 {
-       compatible = "renesas,em-uart";
-       reg = <0xe1020000 0x38>;
-       interrupts = <0 8 0>;
-       clocks = <&usia_u0_sclk>;
-       clock-names = "sclk";
-};
-
-Example of clock-tree description:
-
- This describes a clock path in the clock tree
-  c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
-
-smu@e0110000 {
-       compatible = "renesas,emev2-smu";
-       reg = <0xe0110000 0x10000>;
-       #address-cells = <2>;
-       #size-cells = <0>;
-
-       c32ki: c32ki {
-               compatible = "fixed-clock";
-               clock-frequency = <32768>;
-               #clock-cells = <0>;
-       };
-       pll3_fo: pll3_fo {
-               compatible = "fixed-factor-clock";
-               clocks = <&c32ki>;
-               clock-div = <1>;
-               clock-mult = <7000>;
-               #clock-cells = <0>;
-       };
-       usia_u0_sclkdiv: usia_u0_sclkdiv {
-               compatible = "renesas,emev2-smu-clkdiv";
-               reg = <0x610 0>;
-               clocks = <&pll3_fo>;
-               #clock-cells = <0>;
-       };
-       usia_u0_sclk: usia_u0_sclk {
-               compatible = "renesas,emev2-smu-gclk";
-               reg = <0x4a0 1>;
-               clocks = <&usia_u0_sclkdiv>;
-               #clock-cells = <0>;
-       };
-};

diff --git a/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt
new file mode 100644 (file)
index 0000000..268ca61
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt
@@ -0,0 +1,98 @@
+Device tree Clock bindings for Renesas EMMA Mobile EV2
+
+This binding uses the common clock binding.
+
+* SMU
+System Management Unit described in user's manual R19UH0037EJ1000_SMU.
+This is not a clock provider, but clocks under SMU depend on it.
+
+Required properties:
+- compatible: Should be "renesas,emev2-smu"
+- reg: Address and Size of SMU registers
+
+* SMU_CLKDIV
+Function block with an input mux and a divider, which corresponds to
+"Serial clock generator" in fig."Clock System Overview" of the manual,
+and "xxx frequency division setting register" (XXXCLKDIV) registers.
+This makes internal (neither input nor output) clock that is provided
+to input of xxxGCLK block.
+
+Required properties:
+- compatible: Should be "renesas,emev2-smu-clkdiv"
+- reg: Byte offset from SMU base and Bit position in the register
+- clocks: Parent clocks. Input clocks as described in clock-bindings.txt
+- #clock-cells: Should be <0>
+
+* SMU_GCLK
+Clock gating node shown as "Clock stop processing block" in the
+fig."Clock System Overview" of the manual.
+Registers are "xxx clock gate control register" (XXXGCLKCTRL).
+
+Required properties:
+- compatible: Should be "renesas,emev2-smu-gclk"
+- reg: Byte offset from SMU base and Bit position in the register
+- clocks: Input clock as described in clock-bindings.txt
+- #clock-cells: Should be <0>
+
+Example of provider:
+
+usia_u0_sclkdiv: usia_u0_sclkdiv {
+       compatible = "renesas,emev2-smu-clkdiv";
+       reg = <0x610 0>;
+       clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;
+       #clock-cells = <0>;
+};
+
+usia_u0_sclk: usia_u0_sclk {
+       compatible = "renesas,emev2-smu-gclk";
+       reg = <0x4a0 1>;
+       clocks = <&usia_u0_sclkdiv>;
+       #clock-cells = <0>;
+};
+
+Example of consumer:
+
+serial@e1020000 {
+       compatible = "renesas,em-uart";
+       reg = <0xe1020000 0x38>;
+       interrupts = <0 8 0>;
+       clocks = <&usia_u0_sclk>;
+       clock-names = "sclk";
+};
+
+Example of clock-tree description:
+
+ This describes a clock path in the clock tree
+  c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
+
+smu@e0110000 {
+       compatible = "renesas,emev2-smu";
+       reg = <0xe0110000 0x10000>;
+       #address-cells = <2>;
+       #size-cells = <0>;
+
+       c32ki: c32ki {
+               compatible = "fixed-clock";
+               clock-frequency = <32768>;
+               #clock-cells = <0>;
+       };
+       pll3_fo: pll3_fo {
+               compatible = "fixed-factor-clock";
+               clocks = <&c32ki>;
+               clock-div = <1>;
+               clock-mult = <7000>;
+               #clock-cells = <0>;
+       };
+       usia_u0_sclkdiv: usia_u0_sclkdiv {
+               compatible = "renesas,emev2-smu-clkdiv";
+               reg = <0x610 0>;
+               clocks = <&pll3_fo>;
+               #clock-cells = <0>;
+       };
+       usia_u0_sclk: usia_u0_sclk {
+               compatible = "renesas,emev2-smu-gclk";
+               reg = <0x4a0 1>;
+               clocks = <&usia_u0_sclkdiv>;
+               #clock-cells = <0>;
+       };
+};