return ret;
}
+
+void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,
+ const char *fmt, ...)
+{
+ struct va_format vaf;
+ va_list args;
+
+ va_start(args, fmt);
+ vaf.fmt = fmt;
+ vaf.va = &args;
+
+ if (amdgpu_ras_event_id_is_valid(adev, event_id))
+ dev_printk(KERN_INFO, adev->dev, "{%llu}%pV", event_id, &vaf);
+ else
+ dev_printk(KERN_INFO, adev->dev, "%pV", &vaf);
+
+ va_end(args);
+}
/* The high three bits indicates socketid */
#define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK)
-#define RAS_EVENT_LOG(_adev, _id, _fmt, ...) \
-do { \
- if (amdgpu_ras_event_id_is_valid((_adev), (_id))) \
- dev_info((_adev)->dev, "{%llu}" _fmt, (_id), ##__VA_ARGS__); \
- else \
- dev_info((_adev)->dev, _fmt, ##__VA_ARGS__); \
-} while (0)
+#define RAS_EVENT_LOG(adev, id, fmt, ...) \
+ amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__);
enum amdgpu_ras_block {
AMDGPU_RAS_BLOCK__UMC = 0,
enum amdgpu_ras_block block, uint16_t pasid,
pasid_notify pasid_fn, void *data, uint32_t reset);
+__printf(3, 4)
+void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,
+ const char *fmt, ...);
+
#endif