drm/i915/cx0: Remove bus reset after every c10 transaction

C10 phy timeouts occur on xe3lpd if the c10 bus is reset every
transaction. Although not required by BSPEC bus resets were added for
prior platforms as a workaround. Starting with xe3_lpd this bus reset is
not necessary.

Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241028193015.3241858-6-clinton.a.taylor@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a404873..8ad1910 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -224,7 +224,8 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
         * down and let the message bus to end up
         * in a known state
         */
-       intel_cx0_bus_reset(encoder, lane);
+       if (DISPLAY_VER(i915) < 30)
+               intel_cx0_bus_reset(encoder, lane);
 
        return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
 }
@@ -313,7 +314,8 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
         * down and let the message bus to end up
         * in a known state
         */
-       intel_cx0_bus_reset(encoder, lane);
+       if (DISPLAY_VER(i915) < 30)
+               intel_cx0_bus_reset(encoder, lane);
 
        return 0;
 }