drm/i915/adlp+/dp_mst: Align master transcoder disabling with spec wrt. DP2 config

On ADLP+ during modeset disabling, disable the DP2 configuration for MST
master transcoders as required by the specification.

Bspec: 55424, 54128, 65448, 68849
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030192313.4030617-6-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3198353..769bd1f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3097,6 +3097,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
 
        intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false);
 
+       intel_ddi_config_transcoder_dp2(old_crtc_state, false);
+
        /*
         * From TGL spec: "If single stream or multi-stream master transcoder:
         * Configure Transcoder Clock select to direct no clock to the