wlcore/wl12xx/wl18xx: don't use TX align quirk for wl127x
authorLuciano Coelho <coelho@ti.com>
Mon, 4 Jun 2012 21:02:25 +0000 (00:02 +0300)
committerLuciano Coelho <coelho@ti.com>
Tue, 5 Jun 2012 13:07:16 +0000 (16:07 +0300)
Commit 4afc37 (wlcore: reorder identify_chip and get_hw_info) broke
support for wl127x chips.

When we moved the identify_chip operation to an earlier stage (ie. to
the probe function), we broke wl127x support because during HW init we
would set the WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN.

To avoid this, set this quirk in the identify_chip operations and only
force it to be unset if the bus module doesn't support it.  We were
doing the opposite and setting the flag if the bus module supports it.

Signed-off-by: Luciano Coelho <coelho@ti.com>
drivers/net/wireless/ti/wl12xx/main.c
drivers/net/wireless/ti/wl18xx/main.c
drivers/net/wireless/ti/wlcore/main.c

index ba5afa4..67974f6 100644 (file)
@@ -625,9 +625,6 @@ static int wl12xx_identify_chip(struct wl1271 *wl)
                wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
                               wl->chip.id);
 
-               /* clear the alignment quirk, since we don't support it */
-               wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
-
                wl->quirks |= WLCORE_QUIRK_LEGACY_NVS;
                wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
                wl->mr_fw_name = WL127X_FW_NAME_MULTI;
@@ -643,9 +640,6 @@ static int wl12xx_identify_chip(struct wl1271 *wl)
                wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
                             wl->chip.id);
 
-               /* clear the alignment quirk, since we don't support it */
-               wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
-
                wl->quirks |= WLCORE_QUIRK_LEGACY_NVS;
                wl->plt_fw_name = WL127X_PLT_FW_NAME;
                wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
@@ -664,6 +658,10 @@ static int wl12xx_identify_chip(struct wl1271 *wl)
                wl->plt_fw_name = WL128X_PLT_FW_NAME;
                wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
                wl->mr_fw_name = WL128X_FW_NAME_MULTI;
+
+               /* wl128x requires TX blocksize alignment */
+               wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
+
                break;
        case CHIP_ID_1283_PG10:
        default:
index dda9c18..2e9b3cb 100644 (file)
@@ -591,8 +591,9 @@ static int wl18xx_identify_chip(struct wl1271 *wl)
                /* wl18xx uses the same firmware for PLT */
                wl->plt_fw_name = WL18XX_FW_NAME;
                wl->quirks |= WLCORE_QUIRK_NO_ELP |
-                             WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
-                             WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN;
+                       WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
+                       WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
+                       WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
 
                /* PG 1.0 has some problems with MCS_13, so disable it */
                wl->ht_cap.mcs.rx_mask[1] &= ~BIT(5);
index 00a4821..af00dab 100644 (file)
@@ -960,9 +960,12 @@ static int wl12xx_chip_wakeup(struct wl1271 *wl, bool plt)
         * simplify the code and since the performance impact is
         * negligible, we use the same block size for all different
         * chip types.
+        *
+        * Check if the bus supports blocksize alignment and, if it
+        * doesn't, make sure we don't have the quirk.
         */
-       if (wl1271_set_block_size(wl))
-               wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
+       if (!wl1271_set_block_size(wl))
+               wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
 
        /* TODO: make sure the lower driver has set things up correctly */