staging: media: tegra-video: add hooks for planar YUV and H/V flip

Tegra20 supports planar YUV422 capture, which can be implemented by writing
U and V base address registers in addition to the "main" base buffer
address register.

It also supports H and V flip, which among others requires to write the
start address (i.e. the 1st offset to write, at the end of the buffer or
line) in more registers for Y and, for planar formats, U and V.

Add minimal hooks in VI to allow per-SoC optional support to those
features:

 - variables in struct tegra_vi for the U and V buffer base offsets
 - variables in struct tegra_vi for the Y, U and V buffer start offsets
 - an optional per-soc VI operation to compute those values on queue setup

Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>

diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c
index caad176..0d02468 100644 (file)
--- a/drivers/staging/media/tegra-video/vi.c
+++ b/drivers/staging/media/tegra-video/vi.c
@@ -102,6 +102,7 @@ tegra_get_format_by_fourcc(struct tegra_vi *vi, u32 fourcc)
 /*
  * videobuf2 queue operations
  */
+
 static int tegra_channel_queue_setup(struct vb2_queue *vq,
                                     unsigned int *nbuffers,
                                     unsigned int *nplanes,
@@ -117,6 +118,9 @@ static int tegra_channel_queue_setup(struct vb2_queue *vq,
        sizes[0] = chan->format.sizeimage;
        alloc_devs[0] = chan->vi->dev;
 
+       if (chan->vi->ops->channel_queue_setup)
+               chan->vi->ops->channel_queue_setup(chan);
+
        return 0;
 }
 

diff --git a/drivers/staging/media/tegra-video/vi.h b/drivers/staging/media/tegra-video/vi.h
index 02f940f..cadf80b 100644 (file)
--- a/drivers/staging/media/tegra-video/vi.h
+++ b/drivers/staging/media/tegra-video/vi.h
@@ -47,6 +47,7 @@ struct tegra_vi_channel;
  * @channel_host1x_syncpt_free: free all synchronization points
  * @vi_fmt_align: modify `pix` to fit the hardware alignment
  *             requirements and fill image geometry
+ * @channel_queue_setup: additional operations at the end of vb2_ops::queue_setup
  * @vi_start_streaming: starts media pipeline, subdevice streaming, sets up
  *             VI for capture and runs capture start and capture finish
  *             kthreads for capturing frames to buffer and returns them back.
@@ -58,6 +59,7 @@ struct tegra_vi_ops {
        int (*channel_host1x_syncpt_init)(struct tegra_vi_channel *chan);
        void (*channel_host1x_syncpt_free)(struct tegra_vi_channel *chan);
        void (*vi_fmt_align)(struct v4l2_pix_format *pix, unsigned int bpp);
+       void (*channel_queue_setup)(struct tegra_vi_channel *chan);
        int (*vi_start_streaming)(struct vb2_queue *vq, u32 count);
        void (*vi_stop_streaming)(struct vb2_queue *vq);
 };
@@ -148,6 +150,12 @@ struct tegra_vi {
  * @queue: vb2 buffers queue
  * @sequence: V4L2 buffers sequence number
  *
+ * @addr_offset_u: U plane base address, relative to buffer base address (only for planar)
+ * @addr_offset_v: V plane base address, relative to buffer base address (only for planar)
+ * @start_offset:   1st Y byte to write, relative to buffer base address (for H/V flip)
+ * @start_offset_u: 1st U byte to write, relative to buffer base address (for H/V flip)
+ * @start_offset_v: 1st V byte to write, relative to buffer base address (for H/V flip)
+ *
  * @capture: list of queued buffers for capture
  * @start_lock: protects the capture queued list
  * @done: list of capture done queued buffers
@@ -189,6 +197,12 @@ struct tegra_vi_channel {
        struct vb2_queue queue;
        u32 sequence;
 
+       unsigned int addr_offset_u;
+       unsigned int addr_offset_v;
+       unsigned int start_offset;
+       unsigned int start_offset_u;
+       unsigned int start_offset_v;
+
        struct list_head capture;
        /* protects the capture queued list */
        spinlock_t start_lock;