arm64: dts: qcom: qdu1000: correct LLCC reg entries
authorKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tue, 7 Nov 2023 08:04:16 +0000 (09:04 +0100)
committerBjorn Andersson <andersson@kernel.org>
Thu, 7 Dec 2023 16:14:01 +0000 (08:14 -0800)
According to bindings and Linux driver there is no
"multi_channel_register" address space for LLCC.  The first "reg" entry
is supposed to be llcc0_base since commit 43aa006e074c ("dt-bindings:
arm: msm: Fix register regions used for LLCC banks"):

  qdu1000-idp.dtb: system-cache-controller@19200000: reg: [[0, 421527552, 0, 14155776], [0, 438304768, 0, 524288], [0, 572293416, 0, 4]] is too long
  qdu1000-idp.dtb: system-cache-controller@19200000: reg-names:0: 'llcc0_base' was expected
  qdu1000-idp.dtb: system-cache-controller@19200000: reg-names: ['llcc_base', 'llcc_broadcast_base', 'multi_channel_register'] is too long

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Mukesh Ojha <quic_mojha@quicinc.com>
Link: https://lore.kernel.org/r/20231107080417.16700-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm64/boot/dts/qcom/qdu1000.dtsi

index 1c0e5d2..618a101 100644 (file)
                system-cache-controller@19200000 {
                        compatible = "qcom,qdu1000-llcc";
                        reg = <0 0x19200000 0 0xd80000>,
-                             <0 0x1a200000 0 0x80000>,
-                             <0 0x221c8128 0 0x4>;
-                       reg-names = "llcc_base",
-                                   "llcc_broadcast_base",
-                                   "multi_channel_register";
+                             <0 0x1a200000 0 0x80000>;
+                       reg-names = "llcc0_base",
+                                   "llcc_broadcast_base";
                        interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
                        multi-ch-bit-off = <24 2>;
                };