powerpc/reg: use ASM_FTR_IFSET() instead of opencoding fixup.

mftb() includes a feature fixup for CELL ppc.

Use ASM_FTR_IFSET() macro instead of opencoding the setup
of the fixup sections.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/ac19713826fa55e9e7bfe3100c5a7b1712ab9526.1566999711.git.christophe.leroy@c-s.fr

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index b3cbb11..f3f3688 100644 (file)
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1384,19 +1384,9 @@ static inline void msr_check_and_clear(unsigned long bits)
 #define mftb()         ({unsigned long rval;                           \
                        asm volatile(                                   \
                                "90:    mfspr %0, %2;\n"                \
-                               "97:    cmpwi %0,0;\n"                  \
-                               "       beq- 90b;\n"                    \
-                               "99:\n"                                 \
-                               ".section __ftr_fixup,\"a\"\n"          \
-                               ".align 3\n"                            \
-                               "98:\n"                                 \
-                               "       .8byte %1\n"                    \
-                               "       .8byte %1\n"                    \
-                               "       .8byte 97b-98b\n"               \
-                               "       .8byte 99b-98b\n"               \
-                               "       .8byte 0\n"                     \
-                               "       .8byte 0\n"                     \
-                               ".previous"                             \
+                               ASM_FTR_IFSET(                          \
+                                       "97:    cmpwi %0,0;\n"          \
+                                       "       beq- 90b;\n", "", %1)   \
                        : "=r" (rval) \
                        : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
                        rval;})