cxl/pci: Rename pci.h to cxlpci.h

Similar to the mem.h rename, if the core wants to reuse definitions from
drivers/cxl/pci.h it is unable to use <pci.h> as that collides with
archs that have an arch/$arch/include/asm/pci.h, like MIPS.

Reported-by: kernel test robot <lkp@intel.com>
Acked-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/164298422510.3018233.14693126572756675563.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index 5d848b7..8d4fd75 100644 (file)
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -6,8 +6,8 @@
 #include <linux/kernel.h>
 #include <linux/acpi.h>
 #include <linux/pci.h>
+#include "cxlpci.h"
 #include "cxl.h"
-#include "pci.h"
 
 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
 #define CFMWS_INTERLEAVE_WAYS(x)       (1 << (x)->interleave_ways)

diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 12a6cbd..65d7f58 100644 (file)
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -5,7 +5,7 @@
 #include <linux/slab.h>
 #include <linux/pci.h>
 #include <cxlmem.h>
-#include <pci.h>
+#include <cxlpci.h>
 
 /**
  * DOC: cxl registers

diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
new file mode 100644 (file)
index 0000000..eb00f59
--- /dev/null
+++ b/drivers/cxl/cxlpci.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
+#ifndef __CXL_PCI_H__
+#define __CXL_PCI_H__
+#include "cxl.h"
+
+#define CXL_MEMORY_PROGIF      0x10
+
+/*
+ * See section 8.1 Configuration Space Registers in the CXL 2.0
+ * Specification. Names are taken straight from the specification with "CXL" and
+ * "DVSEC" redundancies removed. When obvious, abbreviations may be used.
+ */
+#define PCI_DVSEC_HEADER1_LENGTH_MASK  GENMASK(31, 20)
+#define PCI_DVSEC_VENDOR_ID_CXL                0x1E98
+
+/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
+#define CXL_DVSEC_PCIE_DEVICE                                  0
+
+/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */
+#define CXL_DVSEC_FUNCTION_MAP                                 2
+
+/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
+#define CXL_DVSEC_PORT_EXTENSIONS                              3
+
+/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */
+#define CXL_DVSEC_PORT_GPF                                     4
+
+/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */
+#define CXL_DVSEC_DEVICE_GPF                                   5
+
+/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */
+#define CXL_DVSEC_PCIE_FLEXBUS_PORT                            7
+
+/* CXL 2.0 8.1.9: Register Locator DVSEC */
+#define CXL_DVSEC_REG_LOCATOR                                  8
+#define   CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET                  0xC
+#define     CXL_DVSEC_REG_LOCATOR_BIR_MASK                     GENMASK(2, 0)
+#define            CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK                 GENMASK(15, 8)
+#define     CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK           GENMASK(31, 16)
+
+/* Register Block Identifier (RBI) */
+enum cxl_regloc_type {
+       CXL_REGLOC_RBI_EMPTY = 0,
+       CXL_REGLOC_RBI_COMPONENT,
+       CXL_REGLOC_RBI_VIRT,
+       CXL_REGLOC_RBI_MEMDEV,
+       CXL_REGLOC_RBI_TYPES
+};
+
+static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
+                                                struct cxl_register_map *map)
+{
+       if (map->block_offset == U64_MAX)
+               return CXL_RESOURCE_NONE;
+
+       return pci_resource_start(pdev, map->barno) + map->block_offset;
+}
+
+#endif /* __CXL_PCI_H__ */

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 7d5f0c8..8b435b8 100644 (file)
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -10,7 +10,7 @@
 #include <linux/pci.h>
 #include <linux/io.h>
 #include "cxlmem.h"
-#include "pci.h"
+#include "cxlpci.h"
 #include "cxl.h"
 
 /**

diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h
deleted file mode 100644 (file)
index 0623bb8..0000000
--- a/drivers/cxl/pci.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
-#ifndef __CXL_PCI_H__
-#define __CXL_PCI_H__
-
-#define CXL_MEMORY_PROGIF      0x10
-
-/*
- * See section 8.1 Configuration Space Registers in the CXL 2.0
- * Specification. Names are taken straight from the specification with "CXL" and
- * "DVSEC" redundancies removed. When obvious, abbreviations may be used.
- */
-#define PCI_DVSEC_HEADER1_LENGTH_MASK  GENMASK(31, 20)
-#define PCI_DVSEC_VENDOR_ID_CXL                0x1E98
-
-/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
-#define CXL_DVSEC_PCIE_DEVICE                                  0
-
-/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */
-#define CXL_DVSEC_FUNCTION_MAP                                 2
-
-/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
-#define CXL_DVSEC_PORT_EXTENSIONS                              3
-
-/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */
-#define CXL_DVSEC_PORT_GPF                                     4
-
-/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */
-#define CXL_DVSEC_DEVICE_GPF                                   5
-
-/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */
-#define CXL_DVSEC_PCIE_FLEXBUS_PORT                            7
-
-/* CXL 2.0 8.1.9: Register Locator DVSEC */
-#define CXL_DVSEC_REG_LOCATOR                                  8
-#define   CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET                  0xC
-#define     CXL_DVSEC_REG_LOCATOR_BIR_MASK                     GENMASK(2, 0)
-#define            CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK                 GENMASK(15, 8)
-#define     CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK           GENMASK(31, 16)
-
-/* Register Block Identifier (RBI) */
-enum cxl_regloc_type {
-       CXL_REGLOC_RBI_EMPTY = 0,
-       CXL_REGLOC_RBI_COMPONENT,
-       CXL_REGLOC_RBI_VIRT,
-       CXL_REGLOC_RBI_MEMDEV,
-       CXL_REGLOC_RBI_TYPES
-};
-
-static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
-                                                struct cxl_register_map *map)
-{
-       if (map->block_offset == U64_MAX)
-               return CXL_RESOURCE_NONE;
-
-       return pci_resource_start(pdev, map->barno) + map->block_offset;
-}
-
-#endif /* __CXL_PCI_H__ */