drm/amd/amdgpu: enable mgcg on gfx 12.0.1

enable mgcg on gfx 12.0.1

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index fcf2bb0..794e905 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3729,7 +3729,35 @@ static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
                                                       bool enable)
 {
-       /* TODO */
+       uint32_t data, def;
+       if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
+               return;
+
+       /* It is disabled by HW by default */
+       if (enable) {
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
+                       /* 1 - RLC_CGTT_MGCG_OVERRIDE */
+                       def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
+
+                       data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
+                                 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
+                                 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
+
+                       if (def != data)
+                               WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
+               }
+       } else {
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
+                       def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
+
+                       data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
+                                RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
+                                RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
+
+                       if (def != data)
+                               WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
+               }
+       }
 }
 
 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c
index 143329e..30e1660 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc24.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
@@ -402,14 +402,12 @@ static int soc24_common_early_init(void *handle)
                break;
        case IP_VERSION(12, 0, 1):
                adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
-                       AMD_CG_SUPPORT_GFX_CGLS;
+                       AMD_CG_SUPPORT_GFX_CGLS |
+                       AMD_CG_SUPPORT_GFX_MGCG;
                adev->pg_flags = AMD_PG_SUPPORT_VCN |
                        AMD_PG_SUPPORT_JPEG |
                        AMD_PG_SUPPORT_VCN_DPG;
                adev->external_rev_id = adev->rev_id + 0x50;
-               adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
-                               AMD_CG_SUPPORT_GFX_CGLS;
-
                break;
        default:
                /* FIXME: not supported yet */