riscv: Do not fail to build on byte/halfword operations with Zawrs
authorAlexandre Ghiti <alexghiti@rivosinc.com>
Sun, 3 Nov 2024 14:51:42 +0000 (15:51 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Mon, 11 Nov 2024 15:33:09 +0000 (07:33 -0800)
riscv does not have lr instructions on byte and halfword but the
qspinlock implementation actually uses such atomics provided by the
Zabha extension, so those sizes are legitimate.

Then instead of failing to build, just fallback to the !Zawrs path.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20241103145153.105097-3-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/cmpxchg.h

index ebbce13..ac1d7df 100644 (file)
@@ -245,6 +245,11 @@ static __always_inline void __cmpwait(volatile void *ptr,
                 : : : : no_zawrs);
 
        switch (size) {
+       case 1:
+               fallthrough;
+       case 2:
+               /* RISC-V doesn't have lr instructions on byte and half-word. */
+               goto no_zawrs;
        case 4:
                asm volatile(
                "       lr.w    %0, %1\n"