drm/amdgpu: Remove redundant ras->supported

Remove redundant ras->supported, as this value
is also stored in adev->ras_features.

Use adev->ras_features, as that supercedes "ras",
since the latter is its member.

The dependency goes like this:
ras <== adev->ras_features <== hw_supported,
and is read as "ras depends on ras_features, which
depends on hw_supported." The arrows show the flow
of information, i.e. the dependency update.

"hw_supported" should also live in "adev".

Cc: Alexander Deucher <Alexander.Deucher@amd.com>
Cc: John Clements <john.clements@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: John Clements <John.Clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1b60f82..0ed1142 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5108,7 +5108,8 @@ int amdgpu_device_baco_enter(struct drm_device *dev)
        if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
                return -ENOTSUPP;
 
-       if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
+       if (ras && adev->ras_features &&
+           adev->nbio.funcs->enable_doorbell_interrupt)
                adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 
        return amdgpu_dpm_baco_enter(adev);
@@ -5127,7 +5128,8 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
        if (ret)
                return ret;
 
-       if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
+       if (ras && adev->ras_features &&
+           adev->nbio.funcs->enable_doorbell_interrupt)
                adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 
        return 0;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 07e8a7c..7a6a87e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -986,7 +986,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 
                if (!ras)
                        return -EINVAL;
-               ras_mask = (uint64_t)ras->supported << 32 | ras->features;
+               ras_mask = (uint64_t)adev->ras_features << 32 | ras->features;
 
                return copy_to_user(out, &ras_mask,
                                min_t(u64, size, sizeof(ras_mask))) ?

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 17b728d..4885b71 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2146,7 +2146,7 @@ static int psp_load_smu_fw(struct psp_context *psp)
                return 0;
 
        if ((amdgpu_in_reset(adev) &&
-            ras && ras->supported &&
+            ras && adev->ras_features &&
             (adev->asic_type == CHIP_ARCTURUS ||
              adev->asic_type == CHIP_VEGA20)) ||
             (adev->in_runpm &&

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index ebbe2c5..a484ac6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2130,9 +2130,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
        /* hw_supported needs to be aligned with RAS block mask. */
        *hw_supported &= AMDGPU_RAS_BLOCK_MASK;
 
-       *supported = amdgpu_ras_enable == 0 ?
-                       0 : *hw_supported & amdgpu_ras_mask;
-       adev->ras_features = *supported;
+       *supported = amdgpu_ras_enable == 0 ? 0 :
+               *hw_supported & amdgpu_ras_mask;
 }
 
 int amdgpu_ras_init(struct amdgpu_device *adev)
@@ -2154,7 +2153,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
        amdgpu_ras_set_context(adev, con);
 
        amdgpu_ras_check_supported(adev, &con->hw_supported,
-                       &con->supported);
+                                  &adev->ras_features);
        if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
                /* set gfx block ras context feature for VEGA20 Gaming
                 * send ras disable cmd to ras ta during ras late init.
@@ -2210,7 +2209,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
 
        dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
                        "hardware ability[%x] ras_mask[%x]\n",
-                       con->hw_supported, con->supported);
+                       con->hw_supported, adev->ras_features);
        return 0;
 release_con:
        amdgpu_ras_set_context(adev, NULL);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index 60df268..3e830dc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -314,8 +314,6 @@ struct amdgpu_ras {
        /* ras infrastructure */
        /* for ras itself. */
        uint32_t hw_supported;
-       /* for IP to check its ras ability. */
-       uint32_t supported;
        uint32_t features;
        struct list_head head;
        /* sysfs */
@@ -478,7 +476,7 @@ static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
 
        if (block >= AMDGPU_RAS_BLOCK_COUNT)
                return 0;
-       return ras && (ras->supported & (1 << block));
+       return ras && (adev->ras_features & (1 << block));
 }
 
 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index e3f42ad..301695f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -655,7 +655,7 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
        int ret = 0;
 
        /* avoid NBIF got stuck when do RAS recovery in BACO reset */
-       if (ras && ras->supported)
+       if (ras && adev->ras_features)
                adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 
        ret = amdgpu_dpm_baco_reset(adev);
@@ -663,7 +663,7 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
                return ret;
 
        /* re-enable doorbell interrupt after BACO exit */
-       if (ras && ras->supported)
+       if (ras && adev->ras_features)
                adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 
        return 0;
@@ -710,7 +710,8 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
                 * 1. PMFW version > 0x284300: all cases use baco
                 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
                 */
-               if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
+               if (ras && adev->ras_features &&
+                   adev->pm.fw_version <= 0x283400)
                        baco_reset = false;
                break;
        case CHIP_ALDEBARAN:

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
index 2a28c9d..f6b1efc 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
@@ -85,7 +85,7 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
                return 0;
 
        if (state == BACO_STATE_IN) {
-               if (!ras || !ras->supported) {
+               if (!ras || !adev->ras_features) {
                        data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
                        data |= 0x80000000;
                        WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 6274cae..72581e4 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1531,7 +1531,8 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
                                                                      NULL);
                        break;
                default:
-                       if (!ras || !ras->supported || adev->gmc.xgmi.pending_reset) {
+                       if (!ras || !adev->ras_features ||
+                           adev->gmc.xgmi.pending_reset) {
                                if (adev->asic_type == CHIP_ARCTURUS) {
                                        data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
                                        data |= 0x80000000;