net: hns3: use lower_32_bits and upper_32_bits
authorHuazhong Tan <tanhuazhong@huawei.com>
Thu, 28 Jun 2018 04:12:29 +0000 (12:12 +0800)
committerDavid S. Miller <davem@davemloft.net>
Fri, 29 Jun 2018 02:06:34 +0000 (11:06 +0900)
MACRO lower_32_bits and upper_32_bits can help to get bits 0-31
and bits 32-63 of a number, so just use it.

Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c

index 7049d0b..383ecf0 100644 (file)
@@ -123,9 +123,9 @@ static void hclge_cmd_config_regs(struct hclge_cmq_ring *ring)
 
        if (ring->flag == HCLGE_TYPE_CSQ) {
                hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_L_REG,
-                               (u32)dma);
+                               lower_32_bits(dma));
                hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_H_REG,
-                               (u32)((dma >> 31) >> 1));
+                               upper_32_bits(dma));
                hclge_write_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG,
                                (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) |
                                HCLGE_NIC_CMQ_ENABLE);
@@ -133,9 +133,9 @@ static void hclge_cmd_config_regs(struct hclge_cmq_ring *ring)
                hclge_write_dev(hw, HCLGE_NIC_CSQ_HEAD_REG, 0);
        } else {
                hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_L_REG,
-                               (u32)dma);
+                               lower_32_bits(dma));
                hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_H_REG,
-                               (u32)((dma >> 31) >> 1));
+                               upper_32_bits(dma));
                hclge_write_dev(hw, HCLGE_NIC_CRQ_DEPTH_REG,
                                (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) |
                                HCLGE_NIC_CMQ_ENABLE);