drm/xe/bmg: Apply Wa_22019338487
authorVinay Belgaumkar <vinay.belgaumkar@intel.com>
Mon, 1 Jul 2024 23:15:29 +0000 (16:15 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 2 Jul 2024 16:14:00 +0000 (12:14 -0400)
Extend this WA to BMG GT as well. In this case media GT is
not affected. The cap frequencies and max allowed ggtt writes
are different as well. On BMG, we need to do a flush after 1100
GGTT writes, and we need to limit the GT frequency request
to 2133 Mhz during driver load and leave it at that value after
driver unloads.

v3: Fix checkpatch issue

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240701231529.2582452-2-vinay.belgaumkar@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/xe_ggtt.c
drivers/gpu/drm/xe/xe_gt.c
drivers/gpu/drm/xe/xe_guc_pc.c
drivers/gpu/drm/xe/xe_wa_oob.rules

index 883cfc7..0cdbc12 100644 (file)
@@ -74,6 +74,9 @@ static unsigned int probe_gsm_size(struct pci_dev *pdev)
 
 static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
 {
+       struct xe_gt *gt = XE_WA(ggtt->tile->primary_gt, 22019338487) ? ggtt->tile->primary_gt :
+                          ggtt->tile->media_gt;
+       u32 max_gtt_writes = XE_WA(ggtt->tile->primary_gt, 22019338487) ? 1100 : 63;
        /*
         * Wa_22019338487: GMD_ID is a RO register, a dummy write forces gunit
         * to wait for completion of prior GTT writes before letting this through.
@@ -81,8 +84,8 @@ static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
         */
        lockdep_assert_held(&ggtt->lock);
 
-       if ((++ggtt->access_count % 63) == 0) {
-               xe_mmio_write32(ggtt->tile->media_gt, GMD_ID, 0x0);
+       if ((++ggtt->access_count % max_gtt_writes) == 0) {
+               xe_mmio_write32(gt, GMD_ID, 0x0);
                ggtt->access_count = 0;
        }
 }
@@ -218,7 +221,9 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
                ggtt->size = GUC_GGTT_TOP;
 
        if (GRAPHICS_VERx100(xe) >= 1270)
-               ggtt->pt_ops = ggtt->tile->media_gt && XE_WA(ggtt->tile->media_gt, 22019338487) ?
+               ggtt->pt_ops = (ggtt->tile->media_gt &&
+                              XE_WA(ggtt->tile->media_gt, 22019338487)) ||
+                              XE_WA(ggtt->tile->primary_gt, 22019338487) ?
                               &xelpg_pt_wa_ops : &xelpg_pt_ops;
        else
                ggtt->pt_ops = &xelp_pt_ops;
index 29e8ea9..0ba2e2d 100644 (file)
@@ -821,8 +821,7 @@ int xe_gt_sanitize_freq(struct xe_gt *gt)
        int ret = 0;
 
        if ((!xe_uc_fw_is_available(&gt->uc.gsc.fw) ||
-           xe_uc_fw_is_loaded(&gt->uc.gsc.fw)) &&
-           XE_WA(gt, 22019338487))
+            xe_uc_fw_is_loaded(&gt->uc.gsc.fw)) && XE_WA(gt, 22019338487))
                ret = xe_guc_pc_restore_stashed_freq(&gt->uc.guc.pc);
 
        return ret;
index f7b4689..32e93a8 100644 (file)
@@ -46,6 +46,7 @@
 #define GT_FREQUENCY_SCALER    3
 
 #define LNL_MERT_FREQ_CAP      800
+#define BMG_MERT_FREQ_CAP      2133
 
 /**
  * DOC: GuC Power Conservation (PC)
@@ -704,10 +705,14 @@ static u32 pc_max_freq_cap(struct xe_guc_pc *pc)
 {
        struct xe_gt *gt = pc_to_gt(pc);
 
-       if (XE_WA(gt, 22019338487))
-               return min(LNL_MERT_FREQ_CAP, pc->rp0_freq);
-       else
+       if (XE_WA(gt, 22019338487)) {
+               if (xe_gt_is_media_type(gt))
+                       return min(LNL_MERT_FREQ_CAP, pc->rp0_freq);
+               else
+                       return min(BMG_MERT_FREQ_CAP, pc->rp0_freq);
+       } else {
                return pc->rp0_freq;
+       }
 }
 
 /**
index a6b8970..26066be 100644 (file)
@@ -28,3 +28,4 @@
                GRAPHICS_VERSION(2004)
 13011645652    GRAPHICS_VERSION(2004)
 22019338487    MEDIA_VERSION(2000)
+               GRAPHICS_VERSION(2001)