MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option

Use a new config option to enable MIPS 34K ITLB workaround and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 87ef000..632fe8f 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2683,6 +2683,10 @@ config WAR_ICACHE_REFILLS
 config WAR_R10000_LLSC
        bool
 
+# 34K core erratum: "Problems Executing the TLBR Instruction"
+config WAR_MIPS34K_MISSED_ITLB
+       bool
+
 #
 # - Highmem only makes sense for the 32-bit kernel.
 # - The current highmem code will only work properly on physically indexed

diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 52be378..9aa4ea5 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -11,7 +11,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR      \
        OCTEON_IS_MODEL(OCTEON_CN6XXX)

diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 2229c83..4f25636 100644 (file)
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MACH_GENERIC_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index f10efe5..09169cf 100644 (file)
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP22_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index 0a07cf6..1c81d54 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP27_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 9fdc642..ff66adb 100644 (file)
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP28_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index 8a8ec55..b00469a 100644 (file)
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -7,6 +7,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP30_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index 9e8c0c2..c57a9cd 100644 (file)
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP32_WAR_H */

diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 76f7de2..73c9e6d 100644 (file)
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_MIPS_WAR_H */

diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 76f7de2..73c9e6d 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_MIPS_WAR_H */

diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index dcb80b5..c396a31 100644 (file)
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_RM_WAR_H */

diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 0cf25ee..fa9bbc2 100644 (file)
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -24,6 +24,4 @@ extern int sb1250_m3_workaround_needed(void);
 
 #endif
 
-#define MIPS34K_MISSED_ITLB_WAR                0
-
 #endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */

diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 8e572d7..7213d93 100644 (file)
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 1a03fdc..3a7379b 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2716,7 +2716,7 @@ static inline void tlb_probe(void)
 
 static inline void tlb_read(void)
 {
-#if MIPS34K_MISSED_ITLB_WAR
+#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
        int res = 0;
 
        __asm__ __volatile__(
@@ -2738,7 +2738,7 @@ static inline void tlb_read(void)
                "tlbr\n\t"
                ".set reorder");
 
-#if MIPS34K_MISSED_ITLB_WAR
+#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
        if ((res & _ULCAST_(1)))
                __asm__ __volatile__(
                "       .set    push                            \n"

diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index d405ecb..4f4d37b 100644 (file)
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -93,11 +93,4 @@
 #error Check setting of SIBYTE_1956_WAR for your platform
 #endif
 
-/*
- * 34K core erratum: "Problems Executing the TLBR Instruction"
- */
-#ifndef MIPS34K_MISSED_ITLB_WAR
-#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
-#endif
-
 #endif /* _ASM_WAR_H */