drm/nouveau/mc/gf100: define reset masks + intr cleanup
authorBen Skeggs <bskeggs@redhat.com>
Fri, 8 Apr 2016 07:24:40 +0000 (17:24 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 20 May 2016 04:43:04 +0000 (14:43 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h

index ffcdbbd..8397e22 100644 (file)
  */
 #include "priv.h"
 
-const struct nvkm_mc_map
-gf100_mc_intr[] = {
-       { 0x04000000, NVKM_ENGINE_DISP },  /* DISP first, so pageflip timestamps work. */
-       { 0x00000001, NVKM_ENGINE_MSPPP },
-       { 0x00000020, NVKM_ENGINE_CE0 },
-       { 0x00000040, NVKM_ENGINE_CE1 },
-       { 0x00000080, NVKM_ENGINE_CE2 },
-       { 0x00000100, NVKM_ENGINE_FIFO },
-       { 0x00001000, NVKM_ENGINE_GR },
-       { 0x00002000, NVKM_SUBDEV_FB },
+static const struct nvkm_mc_map
+gf100_mc_reset[] = {
+       { 0x00020000, NVKM_ENGINE_MSPDEC },
        { 0x00008000, NVKM_ENGINE_MSVLD },
-       { 0x00040000, NVKM_SUBDEV_THERM },
+       { 0x00001000, NVKM_ENGINE_GR },
+       { 0x00000100, NVKM_ENGINE_FIFO },
+       { 0x00000080, NVKM_ENGINE_CE1 },
+       { 0x00000040, NVKM_ENGINE_CE0 },
+       { 0x00000002, NVKM_ENGINE_MSPPP },
+       {}
+};
+
+static const struct nvkm_mc_map
+gf100_mc_intr[] = {
+       { 0x04000000, NVKM_ENGINE_DISP },
        { 0x00020000, NVKM_ENGINE_MSPDEC },
-       { 0x00100000, NVKM_SUBDEV_TIMER },
-       { 0x00200000, NVKM_SUBDEV_GPIO },       /* PMGR->GPIO */
-       { 0x00200000, NVKM_SUBDEV_I2C },        /* PMGR->I2C/AUX */
-       { 0x01000000, NVKM_SUBDEV_PMU },
-       { 0x02000000, NVKM_SUBDEV_LTC },
-       { 0x08000000, NVKM_SUBDEV_FB },
-       { 0x10000000, NVKM_SUBDEV_BUS },
+       { 0x00008000, NVKM_ENGINE_MSVLD },
+       { 0x00001000, NVKM_ENGINE_GR },
+       { 0x00000100, NVKM_ENGINE_FIFO },
+       { 0x00000040, NVKM_ENGINE_CE1 },
+       { 0x00000020, NVKM_ENGINE_CE0 },
+       { 0x00000001, NVKM_ENGINE_MSPPP },
        { 0x40000000, NVKM_SUBDEV_IBUS },
-       { 0x80000000, NVKM_ENGINE_SW },
+       { 0x10000000, NVKM_SUBDEV_BUS },
+       { 0x08000000, NVKM_SUBDEV_FB },
+       { 0x02000000, NVKM_SUBDEV_LTC },
+       { 0x01000000, NVKM_SUBDEV_PMU },
+       { 0x00200000, NVKM_SUBDEV_GPIO },
+       { 0x00200000, NVKM_SUBDEV_I2C },
+       { 0x00100000, NVKM_SUBDEV_TIMER },
+       { 0x00040000, NVKM_SUBDEV_THERM },
+       { 0x00002000, NVKM_SUBDEV_FB },
        {},
 };
 
@@ -87,6 +97,7 @@ gf100_mc = {
        .intr_unarm = gf100_mc_intr_unarm,
        .intr_rearm = gf100_mc_intr_rearm,
        .intr_mask = gf100_mc_intr_mask,
+       .reset = gf100_mc_reset,
        .unk260 = gf100_mc_unk260,
 };
 
index 07707ea..a389650 100644 (file)
@@ -35,7 +35,6 @@ void nv44_mc_init(struct nvkm_mc *);
 void nv50_mc_init(struct nvkm_mc *);
 extern const struct nvkm_mc_map nv50_mc_intr[];
 
-extern const struct nvkm_mc_map gf100_mc_intr[];
 void gf100_mc_intr_unarm(struct nvkm_mc *);
 void gf100_mc_intr_rearm(struct nvkm_mc *);
 u32 gf100_mc_intr_mask(struct nvkm_mc *);