AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D));
}
+static void amdgpu_dm_plane_add_gfx12_modifiers(struct amdgpu_device *adev,
+ uint64_t **mods, uint64_t *size, uint64_t *capacity)
+{
+ uint64_t mod_64K_2D = AMD_FMT_MOD |
+ AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) |
+ AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D);
+
+ /* 64K without DCC */
+ amdgpu_dm_plane_add_modifier(mods, size, capacity, mod_64K_2D);
+ amdgpu_dm_plane_add_modifier(mods, size, capacity, DRM_FORMAT_MOD_LINEAR);
+}
+
static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
{
uint64_t size = 0, capacity = 128;
case AMDGPU_FAMILY_GC_11_5_0:
amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &size, &capacity);
break;
+ case AMDGPU_FAMILY_GC_12_0_0:
+ amdgpu_dm_plane_add_gfx12_modifiers(adev, mods, &size, &capacity);
+ break;
}
amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);