drm/amd/display: Always enable HPO for DCN4 dGPU
authorLeo (Hanghong) Ma <hanghong.ma@amd.com>
Tue, 11 Jun 2024 18:12:43 +0000 (14:12 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 27 Jun 2024 21:10:37 +0000 (17:10 -0400)
[WHY && HOW]
Some DP EDID CTS tests fail due to HPO disable, and we should keep it
enable on DCN4 dGPU.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

index 42753f5..79a911e 100644 (file)
@@ -408,6 +408,8 @@ void dcn401_init_hw(struct dc *dc)
                REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
        }
 
+       dcn401_setup_hpo_hw_control(hws, true);
+
        if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
                dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
 
index 1cf0608..8159fd8 100644 (file)
@@ -137,7 +137,6 @@ static const struct hwseq_private_funcs dcn401_private_funcs = {
        .program_mall_pipe_config = dcn32_program_mall_pipe_config,
        .update_force_pstate = dcn32_update_force_pstate,
        .update_mall_sel = dcn32_update_mall_sel,
-       .setup_hpo_hw_control = dcn401_setup_hpo_hw_control,
        .calculate_dccg_k1_k2_values = NULL,
        .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,
        .reset_back_end_for_pipe = dcn20_reset_back_end_for_pipe,