drm/amd/display: Remove PIPE_DTO_SRC_SEL programming from set_dtbclk_dto

There are cases where an OTG is remapped from driving a regular HDMI
display to a DP/eDP display. There are also cases where DTBCLK needs to
be enabled for HPO, but DTBCLK DTO programming may be done while OTG is
still enabled which is dangerous as the PIPE_DTO_SRC_SEL programming may
change the pixel clock generator source for a mapped and running OTG and
cause it to hang.

Remove the PIPE_DTO_SRC_SEL programming from this sequence since it is
already done in program_pixel_clk(). Additionally, make sure that
program_pixel_clk sets DTBCLK DTO as source for special HDMI cases.

Cc: stable@vger.kernel.org # 6.11+
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ovidiu Bunea <Ovidiu.Bunea@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index 838d72e..b363f53 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -1392,10 +1392,10 @@ static void dccg35_set_dtbclk_dto(
 
                /* The recommended programming sequence to enable DTBCLK DTO to generate
                 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should
-                * be set only after DTO is enabled
+                * be set only after DTO is enabled.
+                * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the
+                * programming is handled in program_pix_clk() regardless, so it can be removed from here.
                 */
-               REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
-                               PIPE_DTO_SRC_SEL[params->otg_inst], 2);
        } else {
                switch (params->otg_inst) {
                case 0:
@@ -1412,9 +1412,12 @@ static void dccg35_set_dtbclk_dto(
                        break;
                }
 
-               REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
-                               DTBCLK_DTO_ENABLE[params->otg_inst], 0,
-                               PIPE_DTO_SRC_SEL[params->otg_inst], params->is_hdmi ? 0 : 1);
+               /**
+                * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the
+                * programming is handled in program_pix_clk() regardless, so it can be removed from here.
+                */
+               REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
+                               DTBCLK_DTO_ENABLE[params->otg_inst], 0);
 
                REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
                REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);