qed: add support for new port modes

These ports ship on new boards revisions and are supported by newer
firmware versions.

Signed-off-by: Alexander Lobakin <alobakin@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/qlogic/qed/qed_dev.c b/drivers/net/ethernet/qlogic/qed/qed_dev.c
index eaf3782..66a5200 100644 (file)
--- a/drivers/net/ethernet/qlogic/qed/qed_dev.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_dev.c
@@ -4004,6 +4004,11 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
        case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
        case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
        case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
+       case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1:
+       case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1:
+       case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2:
+       case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2:
+       case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4:
                break;
        default:
                DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);

diff --git a/drivers/net/ethernet/qlogic/qed/qed_hsi.h b/drivers/net/ethernet/qlogic/qed/qed_hsi.h
index a4a8455..debc559 100644 (file)
--- a/drivers/net/ethernet/qlogic/qed/qed_hsi.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_hsi.h
@@ -13015,6 +13015,11 @@ struct nvm_cfg1_glob {
 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G                  0xd
 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G                  0xe
 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G                  0xf
+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1           0x11
+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1           0x12
+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2          0x13
+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2          0x14
+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4          0x15
 
        u32                                                     e_lane_cfg1;
        u32                                                     e_lane_cfg2;