drm/i915/irq: Refactor gen11 display interrupt handling

Let's move handling and reset for gen11 display IRQs to their own
functions, similar to how we deal with GT interrupts.  This will make
the top-level functions a bit easier to read and potentially make things
easier to deal with in the future if new platforms wind up needing
different display handling logic.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191202171608.3361125-1-matthew.d.roper@intel.com
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 46a9f7d..a5348f7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2453,6 +2453,25 @@ static inline void gen11_master_intr_enable(void __iomem * const regs)
        raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
 }
 
+static void
+gen11_display_irq_handler(struct drm_i915_private *i915)
+{
+       void __iomem * const regs = i915->uncore.regs;
+       const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
+
+       disable_rpm_wakeref_asserts(&i915->runtime_pm);
+       /*
+        * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
+        * for the display related bits.
+        */
+       raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
+       gen8_de_irq_handler(i915, disp_ctl);
+       raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
+                     GEN11_DISPLAY_IRQ_ENABLE);
+
+       enable_rpm_wakeref_asserts(&i915->runtime_pm);
+}
+
 static __always_inline irqreturn_t
 __gen11_irq_handler(struct drm_i915_private * const i915,
                    u32 (*intr_disable)(void __iomem * const regs),
@@ -2476,21 +2495,8 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
        gen11_gt_irq_handler(gt, master_ctl);
 
        /* IRQs are synced during runtime_suspend, we don't require a wakeref */
-       if (master_ctl & GEN11_DISPLAY_IRQ) {
-               const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
-
-               disable_rpm_wakeref_asserts(&i915->runtime_pm);
-               /*
-                * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
-                * for the display related bits.
-                */
-               raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
-               gen8_de_irq_handler(i915, disp_ctl);
-               raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
-                             GEN11_DISPLAY_IRQ_ENABLE);
-
-               enable_rpm_wakeref_asserts(&i915->runtime_pm);
-       }
+       if (master_ctl & GEN11_DISPLAY_IRQ)
+               gen11_display_irq_handler(i915);
 
        gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
 
@@ -2792,15 +2798,11 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
                ibx_irq_reset(dev_priv);
 }
 
-static void gen11_irq_reset(struct drm_i915_private *dev_priv)
+static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
 {
        struct intel_uncore *uncore = &dev_priv->uncore;
        enum pipe pipe;
 
-       gen11_master_intr_disable(dev_priv->uncore.regs);
-
-       gen11_gt_irq_reset(&dev_priv->gt);
-
        intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
 
        if (INTEL_GEN(dev_priv) >= 12) {
@@ -2829,13 +2831,24 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
        GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
        GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
        GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
-       GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
-       GEN3_IRQ_RESET(uncore, GEN8_PCU_);
 
        if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
                GEN3_IRQ_RESET(uncore, SDE);
 }
 
+static void gen11_irq_reset(struct drm_i915_private *dev_priv)
+{
+       struct intel_uncore *uncore = &dev_priv->uncore;
+
+       gen11_master_intr_disable(dev_priv->uncore.regs);
+
+       gen11_gt_irq_reset(&dev_priv->gt);
+       gen11_display_irq_reset(dev_priv);
+
+       GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+       GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+}
+
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
                                     u8 pipe_mask)
 {