drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on DPU >= 5.0
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fri, 7 Mar 2025 06:24:55 +0000 (08:24 +0200)
committerDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Thu, 1 May 2025 20:39:49 +0000 (23:39 +0300)
Since DPU 5.0 CTL blocks do not require DPU_CTL_SPLIT_DISPLAY, as single
CTL is used for both interfaces. As both RM and encoder now handle
active CTLs, drop that feature bit.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/641592/
Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-7-5d20655f10ca@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

index 6ac97c3..ffc4d42 100644 (file)
@@ -27,17 +27,16 @@ static const struct dpu_mdp_cfg sm8650_mdp = {
        },
 };
 
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sm8650_ctl[] = {
        {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x15000, .len = 0x1000,
-               .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = CTL_SM8550_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x16000, .len = 0x1000,
-               .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = CTL_SM8550_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
index 979527d..c20a26f 100644 (file)
@@ -37,17 +37,16 @@ static const struct dpu_mdp_cfg sm8150_mdp = {
        },
 };
 
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sm8150_ctl[] = {
        {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x1000, .len = 0x1e0,
-               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x1200, .len = 0x1e0,
-               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
index d76b899..5300c24 100644 (file)
@@ -41,12 +41,12 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = {
        {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x1000, .len = 0x1e0,
-               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x1200, .len = 0x1e0,
-               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
index 83db113..614ea64 100644 (file)
@@ -38,12 +38,12 @@ static const struct dpu_ctl_cfg sm7150_ctl[] = {
        {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x1000, .len = 0x1e0,
-               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x1200, .len = 0x1e0,
-               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
index 47e01c3..a86fdb3 100644 (file)
@@ -35,17 +35,16 @@ static const struct dpu_mdp_cfg sm8250_mdp = {
        },
 };
 
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sm8250_ctl[] = {
        {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x1000, .len = 0x1e0,
-               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x1200, .len = 0x1e0,
-               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
index 0c860e8..90e8606 100644 (file)
@@ -35,17 +35,16 @@ static const struct dpu_mdp_cfg sm8350_mdp = {
        },
 };
 
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sm8350_ctl[] = {
        {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x15000, .len = 0x1e8,
-               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .features = CTL_SC7280_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x16000, .len = 0x1e8,
-               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .features = CTL_SC7280_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
index fcee1c3..426a8d7 100644 (file)
@@ -35,17 +35,16 @@ static const struct dpu_mdp_cfg sc8280xp_mdp = {
        },
 };
 
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
        {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x15000, .len = 0x204,
-               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .features = CTL_SC7280_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x16000, .len = 0x204,
-               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .features = CTL_SC7280_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
index 19b2ee8..4612941 100644 (file)
@@ -36,17 +36,16 @@ static const struct dpu_mdp_cfg sm8450_mdp = {
        },
 };
 
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sm8450_ctl[] = {
        {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x15000, .len = 0x204,
-               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .features = CTL_SC7280_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x16000, .len = 0x204,
-               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .features = CTL_SC7280_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
index 4d96ce7..c248b3b 100644 (file)
@@ -35,17 +35,16 @@ static const struct dpu_mdp_cfg sa8775p_mdp = {
        },
 };
 
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sa8775p_ctl[] = {
        {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x15000, .len = 0x204,
-               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .features = CTL_SC7280_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x16000, .len = 0x204,
-               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .features = CTL_SC7280_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
index 24f9884..b1c1707 100644 (file)
@@ -27,17 +27,16 @@ static const struct dpu_mdp_cfg sm8550_mdp = {
        },
 };
 
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sm8550_ctl[] = {
        {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x15000, .len = 0x290,
-               .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = CTL_SM8550_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x16000, .len = 0x290,
-               .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = CTL_SM8550_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
index 6417baa..52cc10a 100644 (file)
@@ -26,17 +26,16 @@ static const struct dpu_mdp_cfg x1e80100_mdp = {
        },
 };
 
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg x1e80100_ctl[] = {
        {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x15000, .len = 0x290,
-               .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = CTL_SM8550_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x16000, .len = 0x290,
-               .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .features = CTL_SM8550_MASK,
                .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,