Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' into...

 - Set clk_init_data pointer inside clk_hw to NULL after registration

* clk-init-destroy:
  clk: Overwrite clk_hw::init with NULL during clk_register()
  clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered
  clk: ti: Don't reference clk_init_data after registration
  clk: qcom: Remove error prints from DFS registration
  rtc: sun6i: Don't reference clk_init_data after registration
  clk: zx296718: Don't reference clk_init_data after registration
  clk: milbeaut: Don't reference clk_init_data after registration
  clk: socfpga: deindent code to proper indentation
  phy: ti: am654-serdes: Don't reference clk_init_data after registration
  clk: sprd: Don't reference clk_init_data after registration
  clk: socfpga: Don't reference clk_init_data after registration
  clk: sirf: Don't reference clk_init_data after registration
  clk: qcom: Don't reference clk_init_data after registration
  clk: meson: axg-audio: Don't reference clk_init_data after registration
  clk: lochnagar: Don't reference clk_init_data after registration
  clk: actions: Don't reference clk_init_data after registration

* clk-doc:
  clk: remove extra ---help--- tags in Kconfig
  clk: add include guard to clk-conf.h
  clk: Document of_parse_clkspec() some more
  clk: Remove extraneous 'for' word in comments

* clk-imx: (32 commits)
  clk: imx: imx8mn: fix pll mux bit
  clk: imx: imx8mm: fix pll mux bit
  clk: imx: clk-pll14xx: unbypass PLL by default
  clk: imx: pll14xx: avoid glitch when set rate
  clk: imx: imx8mn: fix audio pll setting
  clk: imx8mn: Add necessary frequency support for ARM PLL table
  clk: imx8mn: Add missing rate_count assignment for each PLL structure
  clk: imx8mn: fix int pll clk gate
  clk: imx8mn: Add GIC clock
  clk: imx8mn: Fix incorrect parents
  clk: imx8mm: Fix incorrect parents
  clk: imx8mq: Fix sys3 pll references
  clk: imx8mq: Unregister clks when of_clk_add_provider failed
  clk: imx8mm: Unregister clks when of_clk_add_provider failed
  clk: imx8mq: Mark AHB clock as critical
  clk: imx8mn: Keep uart clocks on for early console
  clk: imx: Remove unused function statement
  clk: imx7ulp: Make sure earlycon's clock is enabled
  clk: imx8mm: Switch to platform driver
  clk: imx: imx8mm: fix audio pll setting
  ...

* clk-allwinner:
  clk: sunxi-ng: h6: Allow I2S to change parent rate
  clk: sunxi-ng: v3s: add Allwinner V3 support
  clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
  dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU
  clk: sunxi-ng: v3s: add the missing PLL_DDR1

diff --cc drivers/clk/clk.c
Simple merge

diff --cc drivers/clk/meson/axg-audio.c
index 6be9df1,db0b73d,8028ff6,8028ff6,8028ff6..18b23cd
--- 1/drivers/clk/meson/axg-audio.c
--- 2/drivers/clk/meson/axg-audio.c
--- 3/drivers/clk/meson/axg-audio.c
--- 4/drivers/clk/meson/axg-audio.c
--- 5/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@@@@@ -919,84 -868,54 -868,54 -868,54 -868,54 +919,84 @@@@@@ static int devm_clk_get_enable(struct d
        return 0;
     }
     
 ----static int axg_register_clk_hw_input(struct device *dev,
 ----                                const char *name)
 ++++struct axg_audio_reset_data {
 ++++   struct reset_controller_dev rstc;
 ++++   struct regmap *map;
 ++++   unsigned int offset;
 ++++};
 ++++
 ++++static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
 ++++                                   unsigned long id,
 ++++                                   unsigned int *reg,
 ++++                                   unsigned int *bit)
 +   {
  ---   char *clk_name;
  ---   struct clk_hw *hw;
  ---   int err = 0;
 ++++   unsigned int stride = regmap_get_reg_stride(rst->map);
 +   
  ---   clk_name = kasprintf(GFP_KERNEL, "aud_%s", name);
  ---   if (!clk_name)
  ---           return -ENOMEM;
 ++++   *reg = (id / (stride * BITS_PER_BYTE)) * stride;
 ++++   *reg += rst->offset;
 ++++   *bit = id % (stride * BITS_PER_BYTE);
 ++++}
 +   
  ---   hw = meson_clk_hw_register_input(dev, name, clk_name, 0);
  ---   if (IS_ERR(hw)) {
  ---           /* It is ok if an input clock is missing */
  ---           if (PTR_ERR(hw) == -ENOENT) {
  ---                   dev_dbg(dev, "%s not provided", name);
  ---           } else {
  ---                   err = PTR_ERR(hw);
  ---                   if (err != -EPROBE_DEFER)
  ---                           dev_err(dev, "failed to get %s clock", name);
  ---           }
  ---   }
 ++++static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
 ++++                           unsigned long id, bool assert)
  +++{
 -      char *clk_name;
 -      struct clk_hw *hw;
 -      int err = 0;
 ++++   struct axg_audio_reset_data *rst =
 ++++           container_of(rcdev, struct axg_audio_reset_data, rstc);
 ++++   unsigned int offset, bit;
  +++
 -      clk_name = kasprintf(GFP_KERNEL, "aud_%s", name);
 -      if (!clk_name)
 -              return -ENOMEM;
 ++++   axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
     
 -      hw = meson_clk_hw_register_input(dev, name, clk_name, 0);
 -      if (IS_ERR(hw)) {
 -              /* It is ok if an input clock is missing */
 -              if (PTR_ERR(hw) == -ENOENT) {
 -                      dev_dbg(dev, "%s not provided", name);
 -              } else {
 -                      err = PTR_ERR(hw);
 -                      if (err != -EPROBE_DEFER)
 -                              dev_err(dev, "failed to get %s clock", name);
 -              }
 -      }
  ---   kfree(clk_name);
  ---   return err;
 ++++   regmap_update_bits(rst->map, offset, BIT(bit),
 ++++                   assert ? BIT(bit) : 0);
  +++
 -      kfree(clk_name);
 -      return err;
 ++++   return 0;
     }
     
 ----static int axg_register_clk_hw_inputs(struct device *dev,
 ----                                 const char *basename,
 ----                                 unsigned int count)
 ++++static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
 ++++                           unsigned long id)
     {
 ----   char *name;
 ----   int i, ret;
 ++++   struct axg_audio_reset_data *rst =
 ++++           container_of(rcdev, struct axg_audio_reset_data, rstc);
 ++++   unsigned int val, offset, bit;
     
 ----   for (i = 0; i < count; i++) {
 ----           name = kasprintf(GFP_KERNEL, "%s%d", basename, i);
 ----           if (!name)
 ----                   return -ENOMEM;
 ++++   axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
     
 ----           ret = axg_register_clk_hw_input(dev, name);
 ----           kfree(name);
 ----           if (ret)
 ----                   return ret;
 ----   }
 ++++   regmap_read(rst->map, offset, &val);
     
 ----   return 0;
 ++++   return !!(val & BIT(bit));
  +++}
  +++
 ++++static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
 ++++                           unsigned long id)
 ++++{
 ++++   return axg_audio_reset_update(rcdev, id, true);
 +   }
 +   
 ++++static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
 ++++                           unsigned long id)
 ++++{
 ++++   return axg_audio_reset_update(rcdev, id, false);
 ++++}
 ++++
 ++++static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
 ++++                           unsigned long id)
 ++++{
 ++++   int ret;
 ++++
 ++++   ret = axg_audio_reset_assert(rcdev, id);
 ++++   if (ret)
 ++++           return ret;
 ++++
 ++++   return axg_audio_reset_deassert(rcdev, id);
 ++++}
 ++++
 ++++static const struct reset_control_ops axg_audio_rstc_ops = {
 ++++   .assert = axg_audio_reset_assert,
 ++++   .deassert = axg_audio_reset_deassert,
 ++++   .reset = axg_audio_reset_toggle,
 ++++   .status = axg_audio_reset_status,
 ++++};
 ++++
     static const struct regmap_config axg_audio_regmap_cfg = {
        .reg_bits       = 32,
        .val_bits       = 32,

diff --cc drivers/clk/qcom/clk-rcg2.c
Simple merge

diff --cc drivers/clk/qcom/clk-rpmh.c
Simple merge

diff --cc include/linux/clk-provider.h
Simple merge