crtc);
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
+ struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
const struct drm_plane_state *pstate;
struct drm_plane *plane;
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
struct drm_rect dst, clip = crtc_rect;
- int z_pos;
+ int stage;
if (IS_ERR_OR_NULL(pstate)) {
rc = PTR_ERR(pstate);
return -E2BIG;
}
- z_pos = pstate->normalized_zpos;
-
- /* verify z_pos setting before using it */
- if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) {
+ /* verify stage setting before using it */
+ stage = DPU_STAGE_0 + pstate->normalized_zpos;
+ if (stage >= dpu_kms->catalog->caps->max_mixer_blendstages) {
DPU_ERROR("> %d plane stages assigned\n",
- DPU_STAGE_MAX - DPU_STAGE_0);
+ dpu_kms->catalog->caps->max_mixer_blendstages - DPU_STAGE_0);
return -EINVAL;
}
- to_dpu_plane_state(pstate)->stage = z_pos + DPU_STAGE_0;
- DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos);
+ to_dpu_plane_state(pstate)->stage = stage;
+ DRM_DEBUG_ATOMIC("%s: stage %d\n", dpu_crtc->name, stage);
}