drm/msm/dpu: use PINGPONG_NONE to unbind INTF from PP
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Sun, 4 Jun 2023 03:13:07 +0000 (06:13 +0300)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Wed, 7 Jun 2023 23:08:23 +0000 (02:08 +0300)
Currently the driver passes the PINGPONG index to
dpu_hw_intf_ops::bind_pingpong_blk() callback and uses separate boolean
flag to tell whether INTF should be bound or unbound. Simplify this by
passing PINGPONG_NONE in case of unbinding and drop the flag completely.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/540968/
Link: https://lore.kernel.org/r/20230604031308.894274-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

index f32882e..d219a13 100644 (file)
@@ -2090,8 +2090,8 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
                for (i = 0; i < dpu_enc->num_phys_encs; i++) {
                        if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk)
                                phys_enc->hw_intf->ops.bind_pingpong_blk(
-                                               dpu_enc->phys_encs[i]->hw_intf, false,
-                                               dpu_enc->phys_encs[i]->hw_pp->idx);
+                                               dpu_enc->phys_encs[i]->hw_intf,
+                                               PINGPONG_NONE);
 
                        /* mark INTF flush as pending */
                        if (phys_enc->hw_ctl->ops.update_pending_flush_intf)
index 4f8c918..107f0ef 100644 (file)
@@ -66,7 +66,6 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
        if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk)
                phys_enc->hw_intf->ops.bind_pingpong_blk(
                                phys_enc->hw_intf,
-                               true,
                                phys_enc->hw_pp->idx);
 }
 
@@ -553,8 +552,7 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc)
        if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
                phys_enc->hw_intf->ops.bind_pingpong_blk(
                                phys_enc->hw_intf,
-                               false,
-                               phys_enc->hw_pp->idx);
+                               PINGPONG_NONE);
 
                ctl = phys_enc->hw_ctl;
                ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
index e26629e..662d74d 100644 (file)
@@ -287,7 +287,6 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
        if (phys_enc->hw_intf->ops.bind_pingpong_blk)
                phys_enc->hw_intf->ops.bind_pingpong_blk(
                                phys_enc->hw_intf,
-                               true,
                                phys_enc->hw_pp->idx);
 
        if (phys_enc->hw_pp->merge_3d)
index 5dce182..530f82e 100644 (file)
@@ -267,7 +267,6 @@ static void dpu_hw_intf_setup_prg_fetch(
 
 static void dpu_hw_intf_bind_pingpong_blk(
                struct dpu_hw_intf *intf,
-               bool enable,
                const enum dpu_pingpong pp)
 {
        struct dpu_hw_blk_reg_map *c = &intf->hw;
@@ -276,7 +275,7 @@ static void dpu_hw_intf_bind_pingpong_blk(
        mux_cfg = DPU_REG_READ(c, INTF_MUX);
        mux_cfg &= ~0xf;
 
-       if (enable)
+       if (pp)
                mux_cfg |= (pp - PINGPONG_0) & 0x7;
        else
                mux_cfg |= 0xf;
index 73b0885..33895ec 100644 (file)
@@ -88,7 +88,6 @@ struct dpu_hw_intf_ops {
        u32 (*get_line_count)(struct dpu_hw_intf *intf);
 
        void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
-                       bool enable,
                        const enum dpu_pingpong pp);
        void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count);
        int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);