drm/amd/display: fix bug in force_single_disp_pipe_split

should only lower dpp clock.

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index aa56243..cf474eb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -732,11 +732,14 @@ void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
 void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
                unsigned int pixel_rate_khz)
 {
+       float pixel_rate_mhz = pixel_rate_khz / 1000;
+
        /*
         * force enabling pipe split by lower dpp clock for DPM0 to just
         * below the specify pixel_rate, so bw calc would split pipe.
         */
-       v->max_dppclk[0] = pixel_rate_khz / 1000;
+       if (pixel_rate_mhz < v->max_dppclk[0])
+               v->max_dppclk[0] = pixel_rate_mhz;
 }
 
 void hack_bounding_box(struct dcn_bw_internal_vars *v,