spi: cadence-quadspi: Disable irqs during indirect reads

On architecture where reading the SRAM is slower than the pace at
controller fills it, with interrupt enabled while reading from
SRAM FIFO causes unwanted interrupt storm to CPU.

The inner "bytes to read" loop never exits and waits for the completion
so it is enough to only enable the watermark interrupt when we
are out of bytes to read, which only happens when we start the
transfer (waiting for the FIFO to fill up initially) if the SRAM
is slow.

So only using read watermark interrupt, as the current implementation
doesn't utilize the SRAM full and indirect complete read interrupt.
And disable all the read interrupts while reading from SRAM.

Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Link: https://lore.kernel.org/r/20220813042616.1372110-1-niravkumar.l.rabara@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 72b1a5a..e12ab5b 100644 (file)
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -39,6 +39,7 @@
 #define CQSPI_DISABLE_DAC_MODE         BIT(1)
 #define CQSPI_SUPPORT_EXTERNAL_DMA     BIT(2)
 #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3)
+#define CQSPI_SLOW_SRAM                BIT(4)
 
 /* Capabilities */
 #define CQSPI_SUPPORTS_OCTAL           BIT(0)
@@ -87,6 +88,7 @@ struct cqspi_st {
        bool                    use_dma_read;
        u32                     pd_dev_id;
        bool                    wr_completion;
+       bool                    slow_sram;
 };
 
 struct cqspi_driver_platdata {
@@ -333,7 +335,10 @@ static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
                }
        }
 
-       irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
+       else if (!cqspi->slow_sram)
+               irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
+       else
+               irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR;
 
        if (irq_status)
                complete(&cqspi->transfer_complete);
@@ -673,7 +678,18 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
        /* Clear all interrupts. */
        writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 
-       writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
+       /*
+        * On SoCFPGA platform reading the SRAM is slow due to
+        * hardware limitation and causing read interrupt storm to CPU,
+        * so enabling only watermark interrupt to disable all read
+        * interrupts later as we want to run "bytes to read" loop with
+        * all the read interrupts disabled for max performance.
+        */
+
+       if (!cqspi->slow_sram)
+               writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
+       else
+               writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
 
        reinit_completion(&cqspi->transfer_complete);
        writel(CQSPI_REG_INDIRECTRD_START_MASK,
@@ -684,6 +700,13 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
                                                 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
                        ret = -ETIMEDOUT;
 
+               /*
+                * Disable all read interrupts until
+                * we are out of "bytes to read"
+                */
+               if (cqspi->slow_sram)
+                       writel(0x0, reg_base + CQSPI_REG_IRQMASK);
+
                bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 
                if (ret && bytes_to_read == 0) {
@@ -715,8 +738,11 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
                        bytes_to_read = cqspi_get_rd_sram_level(cqspi);
                }
 
-               if (remaining > 0)
+               if (remaining > 0) {
                        reinit_completion(&cqspi->transfer_complete);
+                       if (cqspi->slow_sram)
+                               writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
+               }
        }
 
        /* Check indirect done status */
@@ -1667,6 +1693,8 @@ static int cqspi_probe(struct platform_device *pdev)
                        cqspi->use_dma_read = true;
                if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
                        cqspi->wr_completion = false;
+               if (ddata->quirks & CQSPI_SLOW_SRAM)
+                       cqspi->slow_sram = true;
 
                if (of_device_is_compatible(pdev->dev.of_node,
                                            "xlnx,versal-ospi-1.0"))
@@ -1779,7 +1807,9 @@ static const struct cqspi_driver_platdata intel_lgm_qspi = {
 };
 
 static const struct cqspi_driver_platdata socfpga_qspi = {
-       .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION,
+       .quirks = CQSPI_DISABLE_DAC_MODE
+                       | CQSPI_NO_SUPPORT_WR_COMPLETION
+                       | CQSPI_SLOW_SRAM,
 };
 
 static const struct cqspi_driver_platdata versal_ospi = {