drm/amd: Pass `adev` to amdgpu_gfx_parse_disable_cu()
authorMario Limonciello (AMD) <superm1@kernel.org>
Mon, 15 Dec 2025 01:12:22 +0000 (19:12 -0600)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 5 Jan 2026 21:59:54 +0000 (16:59 -0500)
In order for messages to be attribute to the correct device
amdgpu_gfx_parse_disable_cu() needs to know what device is being
operated on.  Pass the argument in.

Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

index 1683785..caa2e91 100644 (file)
@@ -100,6 +100,7 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
 /**
  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
  *
+ * @adev: amdgpu device pointer
  * @mask: array in which the per-shader array disable masks will be stored
  * @max_se: number of SEs
  * @max_sh: number of SHs
@@ -107,7 +108,8 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
  * The bitmask of CUs to be disabled in the shader array determined by se and
  * sh is stored in mask[se * max_sh + sh].
  */
-void amdgpu_gfx_parse_disable_cu(unsigned int *mask, unsigned int max_se, unsigned int max_sh)
+void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask,
+                                unsigned int max_se, unsigned int max_sh)
 {
        unsigned int se, sh, cu;
        const char *p;
index 281e03a..585cc8e 100644 (file)
@@ -569,8 +569,8 @@ static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
        return (u32)((1ULL << bit_width) - 1);
 }
 
-void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
-                                unsigned max_sh);
+void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask,
+                                unsigned int max_se, unsigned int max_sh);
 
 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id);
 
index 31c2d33..1081354 100644 (file)
@@ -10114,7 +10114,7 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
        if (!adev || !cu_info)
                return -EINVAL;
 
-       amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
+       amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
 
        mutex_lock(&adev->grbm_idx_mutex);
        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
index 0e5b255..d0ca239 100644 (file)
@@ -7482,7 +7482,7 @@ static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
        if (!adev || !cu_info)
                return -EINVAL;
 
-       amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
+       amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2);
 
        mutex_lock(&adev->grbm_idx_mutex);
        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
index b4dd954..c2e1db2 100644 (file)
@@ -5728,7 +5728,7 @@ static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
        if (!adev || !cu_info)
                return -EINVAL;
 
-       amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
+       amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2);
 
        mutex_lock(&adev->grbm_idx_mutex);
        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
index 64b9491..1da3da6 100644 (file)
@@ -3933,7 +3933,7 @@ static int gfx_v12_1_get_cu_info(struct amdgpu_device *adev,
                return -EINVAL;
        }
 
-       amdgpu_gfx_parse_disable_cu(disable_masks,
+       amdgpu_gfx_parse_disable_cu(adev, disable_masks,
                                    adev->gfx.config.max_shader_engines,
                                    adev->gfx.config.max_sh_per_se);
 
index 8056539..63e6924 100644 (file)
@@ -3555,7 +3555,7 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
 
        memset(cu_info, 0, sizeof(*cu_info));
 
-       amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
+       amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
 
        mutex_lock(&adev->grbm_idx_mutex);
        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
index 9c0bcf8..2fa3a37 100644 (file)
@@ -5063,7 +5063,7 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
 
        memset(cu_info, 0, sizeof(*cu_info));
 
-       amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
+       amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
 
        mutex_lock(&adev->grbm_idx_mutex);
        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
index 5c1f823..4e285ed 100644 (file)
@@ -7084,7 +7084,7 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
        else
                ao_cu_num = adev->gfx.config.max_cu_per_sh;
 
-       amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
+       amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
 
        mutex_lock(&adev->grbm_idx_mutex);
        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
index bb1465a..4eadcf5 100644 (file)
@@ -7762,7 +7762,7 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
                adev->gfx.config.max_sh_per_se > 16)
                return -EINVAL;
 
-       amdgpu_gfx_parse_disable_cu(disable_masks,
+       amdgpu_gfx_parse_disable_cu(adev, disable_masks,
                                    adev->gfx.config.max_shader_engines,
                                    adev->gfx.config.max_sh_per_se);
 
index 4e4d88d..14fc9a3 100644 (file)
@@ -4903,7 +4903,7 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
                adev->gfx.config.max_sh_per_se > 16)
                return -EINVAL;
 
-       amdgpu_gfx_parse_disable_cu(disable_masks,
+       amdgpu_gfx_parse_disable_cu(adev, disable_masks,
                                    adev->gfx.config.max_shader_engines,
                                    adev->gfx.config.max_sh_per_se);