arm64: dts: freescale: Add i.MX8MP EVK board support

Add basic i.MM8MP EVK board support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 6088e36..a6d70b7 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
new file mode 100644 (file)
index 0000000..6df3beb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mp.dtsi"
+
+/ {
+       model = "NXP i.MX8MPlus EVK board";
+       compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
+
+       chosen {
+               stdout-path = &uart2;
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0x0 0x40000000 0 0xc0000000>,
+                     <0x1 0x00000000 0 0xc0000000>;
+       };
+
+       reg_usdhc2_vmmc: regulator-usdhc2 {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+               regulator-name = "VSD_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+};
+
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy1>;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy1: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+                       eee-broken-1000t;
+                       reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+               };
+       };
+};
+
+&snvs_pwrkey {
+       status = "okay";
+};
+
+&uart2 {
+       /* console */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       status = "okay";
+};
+
+&usdhc2 {
+       assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+       assigned-clock-rates = <400000000>;
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+       cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&reg_usdhc2_vmmc>;
+       bus-width = <4>;
+       status = "okay";
+};
+
+&usdhc3 {
+       assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+       assigned-clock-rates = <400000000>;
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};
+
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog>;
+       fsl,ext-reset-output;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+
+       pinctrl_fec: fecgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x3
+                       MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x3
+                       MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x91
+                       MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x91
+                       MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x91
+                       MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x91
+                       MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x91
+                       MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x91
+                       MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x1f
+                       MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x1f
+                       MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x1f
+                       MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x1f
+                       MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x1f
+                       MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x1f
+                       MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02              0x19
+               >;
+       };
+
+       pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19    0x41
+               >;
+       };
+
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX    0x49
+                       MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX    0x49
+               >;
+       };
+
+       pinctrl_usdhc2: usdhc2grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x190
+                       MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d0
+                       MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d0
+                       MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d0
+                       MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d0
+                       MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d0
+                       MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+               >;
+       };
+
+       pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x194
+                       MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d4
+                       MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d4
+                       MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d4
+                       MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d4
+                       MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d4
+                       MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+               >;
+       };
+
+       pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x196
+                       MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d6
+                       MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d6
+                       MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d6
+                       MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d6
+                       MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d6
+                       MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+               >;
+       };
+
+       pinctrl_usdhc2_gpio: usdhc2grp-gpio {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12       0x1c4
+               >;
+       };
+
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x190
+                       MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d0
+                       MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d0
+                       MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d0
+                       MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d0
+                       MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d0
+                       MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d0
+                       MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d0
+                       MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d0
+                       MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d0
+                       MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x190
+               >;
+       };
+
+       pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+               fsl,pins = <
+                       MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x194
+                       MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d4
+                       MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d4
+                       MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d4
+                       MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d4
+                       MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d4
+                       MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d4
+                       MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d4
+                       MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d4
+                       MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d4
+                       MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x194
+               >;
+       };
+
+       pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+               fsl,pins = <
+                       MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x196
+                       MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d6
+                       MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d6
+                       MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d6
+                       MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d6
+                       MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d6
+                       MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d6
+                       MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d6
+                       MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d6
+                       MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d6
+                       MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x196
+               >;
+       };
+
+       pinctrl_wdog: wdoggrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B   0xc6
+               >;
+       };
+};