phy: ti: gmii-sel: Enable USXGMII mode for J7200

TI's J7200 SoC supports USXGMII mode with the CPSW5G instance's MAC Port1.
Add USXGMII mode to the extra_modes member of J7200's SoC data.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241010144845.2555983-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 103b266..e0ca59a 100644 (file)
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -230,7 +230,8 @@ static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
        .use_of_data = true,
        .regfields = phy_gmii_sel_fields_am654,
-       .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
+       .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
+                      BIT(PHY_INTERFACE_MODE_USXGMII),
        .num_ports = 4,
        .num_qsgmii_main_ports = 1,
 };