drm/i915/dg2: add DG2 platform info

DG2 has Xe_LPD display (version 13) and Xe_HPG (version 12.55) graphics.
There are two variants (treated as subplatforms in the code):  DG2-G10
and DG2-G11 that require independent programming in some areas (e.g.,
workarounds).

Bspec: 44472, 44474, 46197, 48028, 48077
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210721223043.834562-4-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 567e8b9..d7f4613 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1392,6 +1392,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
+#define IS_DG2(dev_priv)       IS_PLATFORM(dev_priv, INTEL_DG2)
+#define IS_DG2_G10(dev_priv) \
+       IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
+#define IS_DG2_G11(dev_priv) \
+       IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
                                    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv) \
@@ -1505,6 +1510,28 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_XEHPSDV_GT_STEP(p, since, until) \
        (IS_XEHPSDV(p) && IS_GT_STEP(__i915, since, until))
 
+/*
+ * DG2 hardware steppings are a bit unusual.  The hardware design was forked
+ * to create two variants (G10 and G11) which have distinct workaround sets.
+ * The G11 fork of the DG2 design resets the GT stepping back to "A0" for its
+ * first iteration, even though it's more similar to a G10 B0 stepping in terms
+ * of functionality and workarounds.  However the display stepping does not
+ * reset in the same manner --- a specific stepping like "B0" has a consistent
+ * meaning regardless of whether it belongs to a G10 or G11 DG2.
+ *
+ * TLDR:  All GT workarounds and stepping-specific logic must be applied in
+ * relation to a specific subplatform (G10 or G11), whereas display workarounds
+ * and stepping-specific logic will be applied with a general DG2-wide stepping
+ * number.
+ */
+#define IS_DG2_GT_STEP(__i915, variant, since, until) \
+       (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
+        IS_GT_STEP(__i915, since, until))
+
+#define IS_DG2_DISP_STEP(__i915, since, until) \
+       (IS_DG2(__i915) && \
+        IS_DISPLAY_STEP(__i915, since, until))
+
 #define IS_LP(dev_priv)                (INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)   (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
 #define IS_GEN9_BC(dev_priv)   (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0f8f14e..70e161d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1006,6 +1006,22 @@ static const struct intel_device_info xehpsdv_info = {
        .require_force_probe = 1,
 };
 
+__maybe_unused
+static const struct intel_device_info dg2_info = {
+       XE_HP_FEATURES,
+       XE_HPM_FEATURES,
+       XE_LPD_FEATURES,
+       DGFX_FEATURES,
+       .graphics_rel = 55,
+       .media_rel = 55,
+       PLATFORM(INTEL_DG2),
+       .platform_engine_mask =
+               BIT(RCS0) | BIT(BCS0) |
+               BIT(VECS0) | BIT(VECS1) |
+               BIT(VCS0) | BIT(VCS2),
+       .require_force_probe = 1,
+};
+
 #undef PLATFORM
 
 /*

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index b750f9d..822a26b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -69,6 +69,7 @@ static const char * const platform_names[] = {
        PLATFORM_NAME(ALDERLAKE_S),
        PLATFORM_NAME(ALDERLAKE_P),
        PLATFORM_NAME(XEHPSDV),
+       PLATFORM_NAME(DG2),
 };
 #undef PLATFORM_NAME
 

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4482a73..4447b12 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -89,6 +89,7 @@ enum intel_platform {
        INTEL_ALDERLAKE_S,
        INTEL_ALDERLAKE_P,
        INTEL_XEHPSDV,
+       INTEL_DG2,
        INTEL_MAX_PLATFORMS
 };
 
@@ -107,6 +108,10 @@ enum intel_platform {
 /* CNL/ICL */
 #define INTEL_SUBPLATFORM_PORTF        (0)
 
+/* DG2 */
+#define INTEL_SUBPLATFORM_G10  0
+#define INTEL_SUBPLATFORM_G11  1
+
 enum intel_ppgtt_type {
        INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
        INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,

diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index b99829b..12c92e5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -108,6 +108,18 @@ static const struct intel_step_info xehpsdv_revids[] = {
        [0x8] = { .gt_step = STEP_C0 },
 };
 
+static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
+       [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+       [0x1] = { .gt_step = STEP_A1, .display_step = STEP_A0 },
+       [0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+       [0x8] = { .gt_step = STEP_C0, .display_step = STEP_C0 },
+};
+
+static const struct intel_step_info dg2_g11_revid_step_tbl[] = {
+       [0x0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
+       [0x4] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
+};
+
 void intel_step_init(struct drm_i915_private *i915)
 {
        const struct intel_step_info *revids = NULL;
@@ -115,7 +127,13 @@ void intel_step_init(struct drm_i915_private *i915)
        int revid = INTEL_REVID(i915);
        struct intel_step_info step = {};
 
-       if (IS_XEHPSDV(i915)) {
+       if (IS_DG2_G10(i915)) {
+               revids = dg2_g10_revid_step_tbl;
+               size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
+       } else if (IS_DG2_G11(i915)) {
+               revids = dg2_g11_revid_step_tbl;
+               size = ARRAY_SIZE(dg2_g11_revid_step_tbl);
+       } else if (IS_XEHPSDV(i915)) {
                revids = xehpsdv_revids;
                size = ARRAY_SIZE(xehpsdv_revids);
        } else if (IS_ALDERLAKE_P(i915)) {