ARM: dts: sunxi: Add missing watchdog clocks
authorMaxime Ripard <maxime.ripard@bootlin.com>
Wed, 21 Aug 2019 14:38:35 +0000 (16:38 +0200)
committerMaxime Ripard <maxime.ripard@bootlin.com>
Fri, 23 Aug 2019 10:02:07 +0000 (12:02 +0200)
The watchdog has a clock on all our SoCs, but it wasn't always listed.
Add it to the devicetree where it's missing.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
arch/arm/boot/dts/sun4i-a10.dtsi
arch/arm/boot/dts/sun5i.dtsi
arch/arm/boot/dts/sun6i-a31.dtsi
arch/arm/boot/dts/sun7i-a20.dtsi
arch/arm/boot/dts/sun8i-a23-a33.dtsi
arch/arm/boot/dts/sun8i-r40.dtsi
arch/arm/boot/dts/sun8i-v3s.dtsi
arch/arm/boot/dts/sunxi-h3-h5.dtsi
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

index eed9fcb..ce823c4 100644 (file)
                        compatible = "allwinner,sun4i-a10-wdt";
                        reg = <0x01c20c90 0x10>;
                        interrupts = <24>;
+                       clocks = <&osc24M>;
                };
 
                rtc: rtc@1c20d00 {
index 29a825f..cfb1efc 100644 (file)
                        compatible = "allwinner,sun4i-a10-wdt";
                        reg = <0x01c20c90 0x10>;
                        interrupts = <24>;
+                       clocks = <&osc24M>;
                };
 
                ir0: ir@1c21800 {
index cba8864..bbeb743 100644 (file)
                        compatible = "allwinner,sun6i-a31-wdt";
                        reg = <0x01c20ca0 0x20>;
                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc24M>;
                };
 
                spdif: spdif@1c21000 {
index 747ead9..49380de 100644 (file)
                        compatible = "allwinner,sun4i-a10-wdt";
                        reg = <0x01c20c90 0x10>;
                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc24M>;
                };
 
                rtc: rtc@1c20d00 {
index 954489b..52eed0a 100644 (file)
                        compatible = "allwinner,sun6i-a31-wdt";
                        reg = <0x01c20ca0 0x20>;
                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc24M>;
                };
 
                pwm: pwm@1c21400 {
index f1be554..bde0681 100644 (file)
                        compatible = "allwinner,sun4i-a10-wdt";
                        reg = <0x01c20c90 0x10>;
                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc24M>;
                };
 
                uart0: serial@1c28000 {
index ddbcc28..23ba56d 100644 (file)
                        compatible = "allwinner,sun6i-a31-wdt";
                        reg = <0x01c20ca0 0x20>;
                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc24M>;
                };
 
                lradc: lradc@1c22800 {
index 224e105..eba190b 100644 (file)
                        compatible = "allwinner,sun6i-a31-wdt";
                        reg = <0x01c20ca0 0x20>;
                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc24M>;
                };
 
                spdif: spdif@1c21000 {
index ddb6f11..69128a6 100644 (file)
                                     "allwinner,sun6i-a31-wdt";
                        reg = <0x01c20ca0 0x20>;
                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc24M>;
                };
        };
 };
index 67f920e..4020a1a 100644 (file)
                                     "allwinner,sun6i-a31-wdt";
                        reg = <0x030090a0 0x20>;
                        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc24M>;
                        /* Broken on some H6 boards */
                        status = "disabled";
                };
                                     "allwinner,sun6i-a31-wdt";
                        reg = <0x07020400 0x20>;
                        interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc24M>;
                };
 
                r_intc: interrupt-controller@7021000 {