drm/amd/display: implement shared PSR-SU sink validation helper
authorDavid Zhang <dingchen.zhang@amd.com>
Thu, 24 Mar 2022 03:11:48 +0000 (23:11 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 13 Apr 2022 13:14:22 +0000 (09:14 -0400)
[why]
creating a generic helper for AMD specific PSR-SU sink validation.
Moving the function to the power module to reference it across all
OS.

[how]
- drop PSRSU specific sink validation helper and move to power
  module by reading PSR version and other PSR caps
- call the new helper from linux DM (amdgpu_dm_psr)

Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
drivers/gpu/drm/amd/display/modules/power/power_helpers.c
drivers/gpu/drm/amd/display/modules/power/power_helpers.h

index 0c923a9..13b1751 100644 (file)
@@ -27,6 +27,7 @@
 #include "dc.h"
 #include "dm_helpers.h"
 #include "amdgpu_dm.h"
+#include "modules/power/power_helpers.h"
 
 #ifdef CONFIG_DRM_AMD_DC_DCN
 static bool link_supports_psrsu(struct dc_link *link)
@@ -39,6 +40,9 @@ static bool link_supports_psrsu(struct dc_link *link)
        if (dc->ctx->dce_version < DCN_VERSION_3_1)
                return false;
 
+       if (!is_psr_su_specific_panel(link))
+               return false;
+
        if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP ||
            !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED)
                return false;
@@ -79,7 +83,10 @@ void amdgpu_dm_set_psr_caps(struct dc_link *link)
                link->psr_settings.psr_feature_enabled = true;
        }
 
-       DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled);
+       DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d\n",
+               link->psr_settings.psr_feature_enabled,
+               link->psr_settings.psr_version,
+               link->dpcd_caps.psr_info.psr_version);
 
 }
 
index 2b00f33..97928d4 100644 (file)
@@ -784,3 +784,41 @@ bool dmcu_load_iram(struct dmcu *dmcu,
        return result;
 }
 
+/*
+ * is_psr_su_specific_panel() - check if sink is AMD vendor-specific PSR-SU
+ * supported eDP device.
+ *
+ * @link: dc link pointer
+ *
+ * Return: true if AMDGPU vendor specific PSR-SU eDP panel
+ */
+bool is_psr_su_specific_panel(struct dc_link *link)
+{
+       if (link->dpcd_caps.edp_rev >= DP_EDP_14) {
+               if (link->dpcd_caps.psr_info.psr_version >= DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
+                       return true;
+               /*
+                * Some panels will report PSR capabilities over additional DPCD bits.
+                * Such panels are approved despite reporting only PSR v3, as long as
+                * the additional bits are reported.
+                */
+               if (link->dpcd_caps.psr_info.psr_version < DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)
+                       return false;
+
+               if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) {
+                       /*
+                        * FIXME:
+                        * This is the temporary workaround to disable PSRSU when system turned on
+                        * DSC function on the sepcific sink. Once the PSRSU + DSC is fixed, this
+                        * condition should be removed.
+                        */
+                       if (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)
+                               return false;
+
+                       if (link->dpcd_caps.psr_info.force_psrsu_cap == 0x1)
+                               return true;
+               }
+       }
+
+       return false;
+}
index 2a9f8e2..1a634d8 100644 (file)
@@ -52,4 +52,5 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
                struct dmcu_iram_parameters params,
                unsigned int inst);
 
+bool is_psr_su_specific_panel(struct dc_link *link);
 #endif /* MODULES_POWER_POWER_HELPERS_H_ */