arm64/hw_breakpoint: Directly use ESR_ELx_WNR for an watchpoint exception
authorAnshuman Khandual <anshuman.khandual@arm.com>
Thu, 29 Feb 2024 08:34:31 +0000 (14:04 +0530)
committerCatalin Marinas <catalin.marinas@arm.com>
Fri, 1 Mar 2024 17:36:51 +0000 (17:36 +0000)
Let's use existing ISS encoding for an watchpoint exception i.e ESR_ELx_WNR
This represents an instruction's either writing to or reading from a memory
location during an watchpoint exception. While here this drops non-standard
macro AARCH64_ESR_ACCESS_MASK.

Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20240229083431.356578-1-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/include/asm/hw_breakpoint.h
arch/arm64/kernel/hw_breakpoint.c

index 8405532..bd81cf1 100644 (file)
@@ -59,7 +59,6 @@ static inline void decode_ctrl_reg(u32 reg,
 /* Watchpoints */
 #define ARM_BREAKPOINT_LOAD    1
 #define ARM_BREAKPOINT_STORE   2
-#define AARCH64_ESR_ACCESS_MASK        (1 << 6)
 
 /* Lengths */
 #define ARM_BREAKPOINT_LEN_1   0x1
index 3522563..2f57551 100644 (file)
@@ -21,6 +21,7 @@
 
 #include <asm/current.h>
 #include <asm/debug-monitors.h>
+#include <asm/esr.h>
 #include <asm/hw_breakpoint.h>
 #include <asm/traps.h>
 #include <asm/cputype.h>
@@ -779,7 +780,7 @@ static int watchpoint_handler(unsigned long addr, unsigned long esr,
                 * Check that the access type matches.
                 * 0 => load, otherwise => store
                 */
-               access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W :
+               access = (esr & ESR_ELx_WNR) ? HW_BREAKPOINT_W :
                         HW_BREAKPOINT_R;
                if (!(access & hw_breakpoint_type(wp)))
                        continue;