Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
authorLinus Torvalds <torvalds@linux-foundation.org>
Sun, 17 May 2020 19:33:00 +0000 (12:33 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sun, 17 May 2020 19:33:00 +0000 (12:33 -0700)
Pull clk fixes from Stephen Boyd:
 "Some more clk driver fixes and one core framework fix:

   - A handful of TI driver fixes for bad of_node_put() and incorrect
     parent names

   - Rockchip rk3228 aclk_gpu* creation was interfering with lima GPU
     work so we use a composite clk now

   - Resuming from suspend on Tegra Jetson TK1 was broken because an
     audio PLL calculated an incorrect rate

   - A fix for devicetree probing on IM-PD1 by actually specifying a clk
     name which is required to pass clk registration

   - Avoid list corruption if registration fails for a critical clk"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: ti: clkctrl: convert subclocks to use proper names also
  clk: ti: am33xx: fix RTC clock parent
  clk: ti: clkctrl: Fix Bad of_node_put within clkctrl_get_name
  clk: tegra: Fix initial rate for pll_a on Tegra124
  clk: impd1: Look up clock-output-names
  clk: Unlink clock if failed to prepare or enable
  clk: rockchip: fix incorrect configuration of rk3228 aclk_gpu* clocks

drivers/clk/clk.c
drivers/clk/rockchip/clk-rk3228.c
drivers/clk/tegra/clk-tegra124.c
drivers/clk/ti/clk-33xx.c
drivers/clk/ti/clkctrl.c
drivers/clk/versatile/clk-impd1.c

index 39c59f0..2dfb30b 100644 (file)
@@ -3519,6 +3519,9 @@ static int __clk_core_init(struct clk_core *core)
 out:
        clk_pm_runtime_put(core);
 unlock:
+       if (ret)
+               hlist_del_init(&core->child_node);
+
        clk_prepare_unlock();
 
        if (!ret)
index d17cfb7..d7243c0 100644 (file)
@@ -156,8 +156,6 @@ PNAME(mux_i2s_out_p)                = { "i2s1_pre", "xin12m" };
 PNAME(mux_i2s2_p)              = { "i2s2_src", "i2s2_frac", "xin12m" };
 PNAME(mux_sclk_spdif_p)                = { "sclk_spdif_src", "spdif_frac", "xin12m" };
 
-PNAME(mux_aclk_gpu_pre_p)      = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" };
-
 PNAME(mux_uart0_p)             = { "uart0_src", "uart0_frac", "xin24m" };
 PNAME(mux_uart1_p)             = { "uart1_src", "uart1_frac", "xin24m" };
 PNAME(mux_uart2_p)             = { "uart2_src", "uart2_frac", "xin24m" };
@@ -468,16 +466,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
                        RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,
                        RK2928_CLKGATE_CON(2), 8, GFLAGS),
 
-       GATE(0, "cpll_gpu", "cpll", 0,
-                       RK2928_CLKGATE_CON(3), 13, GFLAGS),
-       GATE(0, "gpll_gpu", "gpll", 0,
-                       RK2928_CLKGATE_CON(3), 13, GFLAGS),
-       GATE(0, "hdmiphy_gpu", "hdmiphy", 0,
-                       RK2928_CLKGATE_CON(3), 13, GFLAGS),
-       GATE(0, "usb480m_gpu", "usb480m", 0,
+       COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_4plls_p, 0,
+                       RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS,
                        RK2928_CLKGATE_CON(3), 13, GFLAGS),
-       COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0,
-                       RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS),
 
        COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
                        RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
@@ -582,8 +573,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
        GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
 
        /* PD_GPU */
-       GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
-       GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),
+       GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
+       GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
 
        /* PD_BUS */
        GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
index 64e229d..e931319 100644 (file)
@@ -1292,7 +1292,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
        { TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
        { TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
        { TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
-       { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 0 },
+       { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 282240000, 0 },
        { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 0 },
        { TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
        { TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
index e001b9b..7dc30dd 100644 (file)
@@ -212,7 +212,7 @@ static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
 };
 
 static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
-       { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
+       { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" },
        { 0 },
 };
 
index 0622660..864c484 100644 (file)
@@ -255,24 +255,53 @@ static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
        return entry->clk;
 }
 
+/* Get clkctrl clock base name based on clkctrl_name or dts node */
+static const char * __init clkctrl_get_clock_name(struct device_node *np,
+                                                 const char *clkctrl_name,
+                                                 int offset, int index,
+                                                 bool legacy_naming)
+{
+       char *clock_name;
+
+       /* l4per-clkctrl:1234:0 style naming based on clkctrl_name */
+       if (clkctrl_name && !legacy_naming) {
+               clock_name = kasprintf(GFP_KERNEL, "%s-clkctrl:%04x:%d",
+                                      clkctrl_name, offset, index);
+               strreplace(clock_name, '_', '-');
+
+               return clock_name;
+       }
+
+       /* l4per:1234:0 old style naming based on clkctrl_name */
+       if (clkctrl_name)
+               return kasprintf(GFP_KERNEL, "%s_cm:clk:%04x:%d",
+                                clkctrl_name, offset, index);
+
+       /* l4per_cm:1234:0 old style naming based on parent node name */
+       if (legacy_naming)
+               return kasprintf(GFP_KERNEL, "%pOFn:clk:%04x:%d",
+                                np->parent, offset, index);
+
+       /* l4per-clkctrl:1234:0 style naming based on node name */
+       return kasprintf(GFP_KERNEL, "%pOFn:%04x:%d", np, offset, index);
+}
+
 static int __init
 _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
                         struct device_node *node, struct clk_hw *clk_hw,
                         u16 offset, u8 bit, const char * const *parents,
-                        int num_parents, const struct clk_ops *ops)
+                        int num_parents, const struct clk_ops *ops,
+                        const char *clkctrl_name)
 {
        struct clk_init_data init = { NULL };
        struct clk *clk;
        struct omap_clkctrl_clk *clkctrl_clk;
        int ret = 0;
 
-       if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
-               init.name = kasprintf(GFP_KERNEL, "%pOFn:%pOFn:%04x:%d",
-                                     node->parent, node, offset,
-                                     bit);
-       else
-               init.name = kasprintf(GFP_KERNEL, "%pOFn:%04x:%d", node,
-                                     offset, bit);
+       init.name = clkctrl_get_clock_name(node, clkctrl_name, offset, bit,
+                                          ti_clk_get_features()->flags &
+                                          TI_CLK_CLKCTRL_COMPAT);
+
        clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
        if (!init.name || !clkctrl_clk) {
                ret = -ENOMEM;
@@ -309,7 +338,7 @@ static void __init
 _ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider,
                       struct device_node *node, u16 offset,
                       const struct omap_clkctrl_bit_data *data,
-                      void __iomem *reg)
+                      void __iomem *reg, const char *clkctrl_name)
 {
        struct clk_hw_omap *clk_hw;
 
@@ -322,7 +351,7 @@ _ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider,
 
        if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset,
                                     data->bit, data->parents, 1,
-                                    &omap_gate_clk_ops))
+                                    &omap_gate_clk_ops, clkctrl_name))
                kfree(clk_hw);
 }
 
@@ -330,7 +359,7 @@ static void __init
 _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
                      struct device_node *node, u16 offset,
                      const struct omap_clkctrl_bit_data *data,
-                     void __iomem *reg)
+                     void __iomem *reg, const char *clkctrl_name)
 {
        struct clk_omap_mux *mux;
        int num_parents = 0;
@@ -357,7 +386,7 @@ _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
 
        if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset,
                                     data->bit, data->parents, num_parents,
-                                    &ti_clk_mux_ops))
+                                    &ti_clk_mux_ops, clkctrl_name))
                kfree(mux);
 }
 
@@ -365,7 +394,7 @@ static void __init
 _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
                      struct device_node *node, u16 offset,
                      const struct omap_clkctrl_bit_data *data,
-                     void __iomem *reg)
+                     void __iomem *reg, const char *clkctrl_name)
 {
        struct clk_omap_divider *div;
        const struct omap_clkctrl_div_data *div_data = data->data;
@@ -393,7 +422,7 @@ _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
 
        if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset,
                                     data->bit, data->parents, 1,
-                                    &ti_clk_divider_ops))
+                                    &ti_clk_divider_ops, clkctrl_name))
                kfree(div);
 }
 
@@ -401,7 +430,7 @@ static void __init
 _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
                          struct device_node *node,
                          const struct omap_clkctrl_reg_data *data,
-                         void __iomem *reg)
+                         void __iomem *reg, const char *clkctrl_name)
 {
        const struct omap_clkctrl_bit_data *bits = data->bit_data;
 
@@ -412,17 +441,17 @@ _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
                switch (bits->type) {
                case TI_CLK_GATE:
                        _ti_clkctrl_setup_gate(provider, node, data->offset,
-                                              bits, reg);
+                                              bits, reg, clkctrl_name);
                        break;
 
                case TI_CLK_DIVIDER:
                        _ti_clkctrl_setup_div(provider, node, data->offset,
-                                             bits, reg);
+                                             bits, reg, clkctrl_name);
                        break;
 
                case TI_CLK_MUX:
                        _ti_clkctrl_setup_mux(provider, node, data->offset,
-                                             bits, reg);
+                                             bits, reg, clkctrl_name);
                        break;
 
                default:
@@ -461,42 +490,10 @@ static char * __init clkctrl_get_name(struct device_node *np)
                        return name;
                }
        }
-       of_node_put(np);
 
        return NULL;
 }
 
-/* Get clkctrl clock base name based on clkctrl_name or dts node */
-static const char * __init clkctrl_get_clock_name(struct device_node *np,
-                                                 const char *clkctrl_name,
-                                                 int offset, int index,
-                                                 bool legacy_naming)
-{
-       char *clock_name;
-
-       /* l4per-clkctrl:1234:0 style naming based on clkctrl_name */
-       if (clkctrl_name && !legacy_naming) {
-               clock_name = kasprintf(GFP_KERNEL, "%s-clkctrl:%04x:%d",
-                                      clkctrl_name, offset, index);
-               strreplace(clock_name, '_', '-');
-
-               return clock_name;
-       }
-
-       /* l4per:1234:0 old style naming based on clkctrl_name */
-       if (clkctrl_name)
-               return kasprintf(GFP_KERNEL, "%s_cm:clk:%04x:%d",
-                                clkctrl_name, offset, index);
-
-       /* l4per_cm:1234:0 old style naming based on parent node name */
-       if (legacy_naming)
-               return kasprintf(GFP_KERNEL, "%pOFn:clk:%04x:%d",
-                                np->parent, offset, index);
-
-       /* l4per-clkctrl:1234:0 style naming based on node name */
-       return kasprintf(GFP_KERNEL, "%pOFn:%04x:%d", np, offset, index);
-}
-
 static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
 {
        struct omap_clkctrl_provider *provider;
@@ -664,7 +661,7 @@ clkdm_found:
                hw->enable_reg.ptr = provider->base + reg_data->offset;
 
                _ti_clkctrl_setup_subclks(provider, node, reg_data,
-                                         hw->enable_reg.ptr);
+                                         hw->enable_reg.ptr, clkctrl_name);
 
                if (reg_data->flags & CLKF_SW_SUP)
                        hw->enable_bit = MODULEMODE_SWCTRL;
index b05da85..f9f4bab 100644 (file)
@@ -206,6 +206,7 @@ static int integrator_impd1_clk_spawn(struct device *dev,
                return -ENODEV;
        }
 
+       of_property_read_string(np, "clock-output-names", &name);
        parent_name = of_clk_get_parent_name(np, 0);
        clk = icst_clk_setup(NULL, desc, name, parent_name, map,
                             ICST_INTEGRATOR_IM_PD1);