S: Maintained
T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
-F: drivers/media/platform/tegra/vde/
+F: drivers/media/platform/nvidia/tegra-vde/
MEDIA DRIVERS FOR RENESAS - CEU
M: Jacopo Mondi <jacopo@jmondi.org>
source "drivers/media/platform/mediatek/mtk-mdp/Kconfig"
source "drivers/media/platform/mediatek/mtk-vcodec/Kconfig"
source "drivers/media/platform/mediatek/mtk-vpu/Kconfig"
+source "drivers/media/platform/nvidia/tegra-vde/Kconfig"
source "drivers/media/platform/nxp/Kconfig"
source "drivers/media/platform/omap/Kconfig"
source "drivers/media/platform/omap3isp/Kconfig"
source "drivers/media/platform/sti/Kconfig"
source "drivers/media/platform/stm32/Kconfig"
source "drivers/media/platform/sunxi/Kconfig"
-source "drivers/media/platform/tegra/vde/Kconfig"
source "drivers/media/platform/ti-vpe/Kconfig"
source "drivers/media/platform/via/Kconfig"
source "drivers/media/platform/xilinx/Kconfig"
obj-y += mediatek/mtk-mdp/
obj-y += mediatek/mtk-vcodec/
obj-y += mediatek/mtk-vpu/
+obj-y += nvidia/tegra-vde/
obj-y += nxp/
obj-y += omap/
obj-y += omap3isp/
obj-y += sti/hva/
obj-y += stm32/
obj-y += sunxi/
-obj-y += tegra/vde/
obj-y += ti-vpe/
obj-y += via/
obj-y += xilinx/
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += tegra-vde/
--- /dev/null
+config VIDEO_TEGRA_VDE
+ tristate "NVIDIA Tegra Video Decoder Engine driver"
+ depends on V4L_MEM2MEM_DRIVERS
+ depends on ARCH_TEGRA || COMPILE_TEST
+ depends on VIDEO_DEV && VIDEO_V4L2
+ select DMA_SHARED_BUFFER
+ select IOMMU_IOVA
+ select MEDIA_CONTROLLER
+ select MEDIA_CONTROLLER_REQUEST_API
+ select SRAM
+ select VIDEOBUF2_DMA_CONTIG
+ select VIDEOBUF2_DMA_SG
+ select V4L2_H264
+ select V4L2_MEM2MEM_DEV
+ help
+ Support for the NVIDIA Tegra video decoder unit.
+ To compile this driver as a module choose m here.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+tegra-vde-y := vde.o iommu.o dmabuf-cache.o h264.o v4l2.o
+obj-$(CONFIG_VIDEO_TEGRA_VDE) += tegra-vde.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NVIDIA Tegra Video decoder driver
+ *
+ * Copyright (C) 2016-2019 GRATE-DRIVER project
+ */
+
+#include <linux/dma-buf.h>
+#include <linux/iova.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <linux/module.h>
+
+#include "vde.h"
+
+MODULE_IMPORT_NS(DMA_BUF);
+
+struct tegra_vde_cache_entry {
+ enum dma_data_direction dma_dir;
+ struct dma_buf_attachment *a;
+ struct delayed_work dwork;
+ struct tegra_vde *vde;
+ struct list_head list;
+ struct sg_table *sgt;
+ struct iova *iova;
+ unsigned int refcnt;
+};
+
+static void tegra_vde_release_entry(struct tegra_vde_cache_entry *entry)
+{
+ struct dma_buf *dmabuf = entry->a->dmabuf;
+
+ WARN_ON_ONCE(entry->refcnt);
+
+ if (entry->vde->domain)
+ tegra_vde_iommu_unmap(entry->vde, entry->iova);
+
+ dma_buf_unmap_attachment(entry->a, entry->sgt, entry->dma_dir);
+ dma_buf_detach(dmabuf, entry->a);
+ dma_buf_put(dmabuf);
+
+ list_del(&entry->list);
+ kfree(entry);
+}
+
+static void tegra_vde_delayed_unmap(struct work_struct *work)
+{
+ struct tegra_vde_cache_entry *entry;
+ struct tegra_vde *vde;
+
+ entry = container_of(work, struct tegra_vde_cache_entry,
+ dwork.work);
+ vde = entry->vde;
+
+ mutex_lock(&vde->map_lock);
+ tegra_vde_release_entry(entry);
+ mutex_unlock(&vde->map_lock);
+}
+
+int tegra_vde_dmabuf_cache_map(struct tegra_vde *vde,
+ struct dma_buf *dmabuf,
+ enum dma_data_direction dma_dir,
+ struct dma_buf_attachment **ap,
+ dma_addr_t *addrp)
+{
+ struct dma_buf_attachment *attachment;
+ struct tegra_vde_cache_entry *entry;
+ struct device *dev = vde->dev;
+ struct sg_table *sgt;
+ struct iova *iova;
+ int err;
+
+ mutex_lock(&vde->map_lock);
+
+ list_for_each_entry(entry, &vde->map_list, list) {
+ if (entry->a->dmabuf != dmabuf)
+ continue;
+
+ if (!cancel_delayed_work(&entry->dwork))
+ continue;
+
+ if (entry->dma_dir != dma_dir)
+ entry->dma_dir = DMA_BIDIRECTIONAL;
+
+ dma_buf_put(dmabuf);
+
+ if (vde->domain)
+ *addrp = iova_dma_addr(&vde->iova, entry->iova);
+ else
+ *addrp = sg_dma_address(entry->sgt->sgl);
+
+ goto ref;
+ }
+
+ attachment = dma_buf_attach(dmabuf, dev);
+ if (IS_ERR(attachment)) {
+ dev_err(dev, "Failed to attach dmabuf\n");
+ err = PTR_ERR(attachment);
+ goto err_unlock;
+ }
+
+ sgt = dma_buf_map_attachment(attachment, dma_dir);
+ if (IS_ERR(sgt)) {
+ dev_err(dev, "Failed to get dmabufs sg_table\n");
+ err = PTR_ERR(sgt);
+ goto err_detach;
+ }
+
+ if (!vde->domain && sgt->nents > 1) {
+ dev_err(dev, "Sparse DMA region is unsupported, please enable IOMMU\n");
+ err = -EINVAL;
+ goto err_unmap;
+ }
+
+ entry = kzalloc(sizeof(*entry), GFP_KERNEL);
+ if (!entry) {
+ err = -ENOMEM;
+ goto err_unmap;
+ }
+
+ if (vde->domain) {
+ err = tegra_vde_iommu_map(vde, sgt, &iova, dmabuf->size);
+ if (err)
+ goto err_free;
+
+ *addrp = iova_dma_addr(&vde->iova, iova);
+ } else {
+ *addrp = sg_dma_address(sgt->sgl);
+ iova = NULL;
+ }
+
+ INIT_DELAYED_WORK(&entry->dwork, tegra_vde_delayed_unmap);
+ list_add(&entry->list, &vde->map_list);
+
+ entry->dma_dir = dma_dir;
+ entry->iova = iova;
+ entry->vde = vde;
+ entry->sgt = sgt;
+ entry->a = attachment;
+ref:
+ entry->refcnt++;
+
+ *ap = entry->a;
+
+ mutex_unlock(&vde->map_lock);
+
+ return 0;
+
+err_free:
+ kfree(entry);
+err_unmap:
+ dma_buf_unmap_attachment(attachment, sgt, dma_dir);
+err_detach:
+ dma_buf_detach(dmabuf, attachment);
+err_unlock:
+ mutex_unlock(&vde->map_lock);
+
+ return err;
+}
+
+void tegra_vde_dmabuf_cache_unmap(struct tegra_vde *vde,
+ struct dma_buf_attachment *a,
+ bool release)
+{
+ struct tegra_vde_cache_entry *entry;
+
+ mutex_lock(&vde->map_lock);
+
+ list_for_each_entry(entry, &vde->map_list, list) {
+ if (entry->a != a)
+ continue;
+
+ WARN_ON_ONCE(!entry->refcnt);
+
+ if (--entry->refcnt == 0) {
+ if (release)
+ tegra_vde_release_entry(entry);
+ else
+ schedule_delayed_work(&entry->dwork, 5 * HZ);
+ }
+ break;
+ }
+
+ mutex_unlock(&vde->map_lock);
+}
+
+void tegra_vde_dmabuf_cache_unmap_sync(struct tegra_vde *vde)
+{
+ struct tegra_vde_cache_entry *entry, *tmp;
+
+ mutex_lock(&vde->map_lock);
+
+ list_for_each_entry_safe(entry, tmp, &vde->map_list, list) {
+ if (entry->refcnt)
+ continue;
+
+ if (!cancel_delayed_work(&entry->dwork))
+ continue;
+
+ tegra_vde_release_entry(entry);
+ }
+
+ mutex_unlock(&vde->map_lock);
+}
+
+void tegra_vde_dmabuf_cache_unmap_all(struct tegra_vde *vde)
+{
+ struct tegra_vde_cache_entry *entry, *tmp;
+
+ mutex_lock(&vde->map_lock);
+
+ while (!list_empty(&vde->map_list)) {
+ list_for_each_entry_safe(entry, tmp, &vde->map_list, list) {
+ if (!cancel_delayed_work(&entry->dwork))
+ continue;
+
+ tegra_vde_release_entry(entry);
+ }
+
+ mutex_unlock(&vde->map_lock);
+ schedule();
+ mutex_lock(&vde->map_lock);
+ }
+
+ mutex_unlock(&vde->map_lock);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NVIDIA Tegra Video decoder driver
+ *
+ * Copyright (C) 2016-2022 Dmitry Osipenko <digetx@gmail.com>
+ *
+ */
+
+#include <linux/iopoll.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#include <media/v4l2-h264.h>
+
+#include "trace.h"
+#include "vde.h"
+
+#define FLAG_B_FRAME 0x1
+#define FLAG_REFERENCE 0x2
+
+struct tegra_vde_h264_frame {
+ unsigned int frame_num;
+ unsigned int flags;
+};
+
+struct tegra_vde_h264_decoder_ctx {
+ unsigned int dpb_frames_nb;
+ unsigned int dpb_ref_frames_with_earlier_poc_nb;
+ unsigned int baseline_profile;
+ unsigned int level_idc;
+ unsigned int log2_max_pic_order_cnt_lsb;
+ unsigned int log2_max_frame_num;
+ unsigned int pic_order_cnt_type;
+ unsigned int direct_8x8_inference_flag;
+ unsigned int pic_width_in_mbs;
+ unsigned int pic_height_in_mbs;
+ unsigned int pic_init_qp;
+ unsigned int deblocking_filter_control_present_flag;
+ unsigned int constrained_intra_pred_flag;
+ unsigned int chroma_qp_index_offset;
+ unsigned int pic_order_present_flag;
+ unsigned int num_ref_idx_l0_active_minus1;
+ unsigned int num_ref_idx_l1_active_minus1;
+};
+
+struct h264_reflists {
+ u8 p[V4L2_H264_NUM_DPB_ENTRIES];
+ u8 b0[V4L2_H264_NUM_DPB_ENTRIES];
+ u8 b1[V4L2_H264_NUM_DPB_ENTRIES];
+};
+
+static int tegra_vde_wait_mbe(struct tegra_vde *vde)
+{
+ u32 tmp;
+
+ return readl_relaxed_poll_timeout(vde->mbe + 0x8C, tmp,
+ tmp >= 0x10, 1, 100);
+}
+
+static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde,
+ unsigned int refs_nb,
+ bool setup_refs)
+{
+ u32 value, frame_idx_enb_mask = 0;
+ unsigned int frame_idx;
+ unsigned int idx;
+ int err;
+
+ tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80);
+ tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80);
+
+ err = tegra_vde_wait_mbe(vde);
+ if (err)
+ return err;
+
+ if (!setup_refs)
+ return 0;
+
+ for (idx = 0, frame_idx = 1; idx < refs_nb; idx++, frame_idx++) {
+ tegra_vde_writel(vde, 0xD0000000 | (frame_idx << 23),
+ vde->mbe, 0x80);
+ tegra_vde_writel(vde, 0xD0200000 | (frame_idx << 23),
+ vde->mbe, 0x80);
+
+ frame_idx_enb_mask |= frame_idx << (6 * (idx % 4));
+
+ if (idx % 4 == 3 || idx == refs_nb - 1) {
+ value = 0xC0000000;
+ value |= (idx >> 2) << 24;
+ value |= frame_idx_enb_mask;
+
+ tegra_vde_writel(vde, value, vde->mbe, 0x80);
+
+ err = tegra_vde_wait_mbe(vde);
+ if (err)
+ return err;
+
+ frame_idx_enb_mask = 0;
+ }
+ }
+
+ return 0;
+}
+
+static void tegra_vde_mbe_set_0xa_reg(struct tegra_vde *vde, int reg, u32 val)
+{
+ tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF),
+ vde->mbe, 0x80);
+ tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16),
+ vde->mbe, 0x80);
+}
+
+static int tegra_vde_wait_bsev(struct tegra_vde *vde, bool wait_dma)
+{
+ struct device *dev = vde->dev;
+ u32 value;
+ int err;
+
+ err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
+ !(value & BIT(2)), 1, 100);
+ if (err) {
+ dev_err(dev, "BSEV unknown bit timeout\n");
+ return err;
+ }
+
+ err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
+ (value & BSE_ICMDQUE_EMPTY), 1, 100);
+ if (err) {
+ dev_err(dev, "BSEV ICMDQUE flush timeout\n");
+ return err;
+ }
+
+ if (!wait_dma)
+ return 0;
+
+ err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
+ !(value & BSE_DMA_BUSY), 1, 1000);
+ if (err) {
+ dev_err(dev, "BSEV DMA timeout\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int tegra_vde_push_to_bsev_icmdqueue(struct tegra_vde *vde,
+ u32 value, bool wait_dma)
+{
+ tegra_vde_writel(vde, value, vde->bsev, ICMDQUE_WR);
+
+ return tegra_vde_wait_bsev(vde, wait_dma);
+}
+
+static void tegra_vde_setup_frameid(struct tegra_vde *vde,
+ struct tegra_video_frame *frame,
+ unsigned int frameid,
+ u32 mbs_width, u32 mbs_height)
+{
+ u32 y_addr = frame ? frame->y_addr : 0x6CDEAD00;
+ u32 cb_addr = frame ? frame->cb_addr : 0x6CDEAD00;
+ u32 cr_addr = frame ? frame->cr_addr : 0x6CDEAD00;
+ u32 value1 = frame ? ((frame->luma_atoms_pitch << 16) | mbs_height) : 0;
+ u32 value2 = frame ? ((frame->chroma_atoms_pitch << 6) | 1) : 0;
+
+ tegra_vde_writel(vde, y_addr >> 8, vde->frameid, 0x000 + frameid * 4);
+ tegra_vde_writel(vde, cb_addr >> 8, vde->frameid, 0x100 + frameid * 4);
+ tegra_vde_writel(vde, cr_addr >> 8, vde->frameid, 0x180 + frameid * 4);
+ tegra_vde_writel(vde, value1, vde->frameid, 0x080 + frameid * 4);
+ tegra_vde_writel(vde, value2, vde->frameid, 0x280 + frameid * 4);
+}
+
+static void tegra_setup_frameidx(struct tegra_vde *vde,
+ struct tegra_video_frame *frames,
+ unsigned int frames_nb,
+ u32 mbs_width, u32 mbs_height)
+{
+ unsigned int idx;
+
+ for (idx = 0; idx < frames_nb; idx++)
+ tegra_vde_setup_frameid(vde, &frames[idx], idx,
+ mbs_width, mbs_height);
+
+ for (; idx < 17; idx++)
+ tegra_vde_setup_frameid(vde, NULL, idx, 0, 0);
+}
+
+static void tegra_vde_setup_iram_entry(struct tegra_vde *vde,
+ unsigned int table,
+ unsigned int row,
+ u32 value1, u32 value2)
+{
+ u32 *iram_tables = vde->iram;
+
+ trace_vde_setup_iram_entry(table, row, value1, value2);
+
+ iram_tables[0x20 * table + row * 2 + 0] = value1;
+ iram_tables[0x20 * table + row * 2 + 1] = value2;
+}
+
+static void tegra_vde_setup_iram_tables(struct tegra_vde *vde,
+ struct tegra_video_frame *dpb_frames,
+ unsigned int ref_frames_nb,
+ unsigned int with_earlier_poc_nb)
+{
+ struct tegra_video_frame *frame;
+ int with_later_poc_nb;
+ u32 value, aux_addr;
+ unsigned int i, k;
+
+ trace_vde_ref_l0(dpb_frames[0].frame_num);
+
+ for (i = 0; i < 16; i++) {
+ if (i < ref_frames_nb) {
+ frame = &dpb_frames[i + 1];
+
+ aux_addr = frame->aux_addr;
+
+ value = (i + 1) << 26;
+ value |= !(frame->flags & FLAG_B_FRAME) << 25;
+ value |= 1 << 24;
+ value |= frame->frame_num;
+ } else {
+ aux_addr = 0x6ADEAD00;
+ value = 0x3f;
+ }
+
+ tegra_vde_setup_iram_entry(vde, 0, i, value, aux_addr);
+ tegra_vde_setup_iram_entry(vde, 1, i, value, aux_addr);
+ tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
+ tegra_vde_setup_iram_entry(vde, 3, i, value, aux_addr);
+ }
+
+ if (!(dpb_frames[0].flags & FLAG_B_FRAME))
+ return;
+
+ if (with_earlier_poc_nb >= ref_frames_nb)
+ return;
+
+ with_later_poc_nb = ref_frames_nb - with_earlier_poc_nb;
+
+ trace_vde_ref_l1(with_later_poc_nb, with_earlier_poc_nb);
+
+ for (i = 0, k = with_earlier_poc_nb; i < with_later_poc_nb; i++, k++) {
+ frame = &dpb_frames[k + 1];
+
+ aux_addr = frame->aux_addr;
+
+ value = (k + 1) << 26;
+ value |= !(frame->flags & FLAG_B_FRAME) << 25;
+ value |= 1 << 24;
+ value |= frame->frame_num;
+
+ tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
+ }
+
+ for (k = 0; i < ref_frames_nb; i++, k++) {
+ frame = &dpb_frames[k + 1];
+
+ aux_addr = frame->aux_addr;
+
+ value = (k + 1) << 26;
+ value |= !(frame->flags & FLAG_B_FRAME) << 25;
+ value |= 1 << 24;
+ value |= frame->frame_num;
+
+ tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
+ }
+}
+
+static int tegra_vde_setup_hw_context(struct tegra_vde *vde,
+ struct tegra_vde_h264_decoder_ctx *ctx,
+ struct tegra_video_frame *dpb_frames,
+ dma_addr_t bitstream_data_addr,
+ size_t bitstream_data_size,
+ unsigned int macroblocks_nb)
+{
+ struct device *dev = vde->dev;
+ u32 value;
+ int err;
+
+ tegra_vde_set_bits(vde, 0x000A, vde->sxe, 0xF0);
+ tegra_vde_set_bits(vde, 0x000B, vde->bsev, CMDQUE_CONTROL);
+ tegra_vde_set_bits(vde, 0x8002, vde->mbe, 0x50);
+ tegra_vde_set_bits(vde, 0x000A, vde->mbe, 0xA0);
+ tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x14);
+ tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x28);
+ tegra_vde_set_bits(vde, 0x0A00, vde->mce, 0x08);
+ tegra_vde_set_bits(vde, 0x000A, vde->tfe, 0x00);
+ tegra_vde_set_bits(vde, 0x0005, vde->vdma, 0x04);
+
+ tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x1C);
+ tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x00);
+ tegra_vde_writel(vde, 0x00000007, vde->vdma, 0x04);
+ tegra_vde_writel(vde, 0x00000007, vde->frameid, 0x200);
+ tegra_vde_writel(vde, 0x00000005, vde->tfe, 0x04);
+ tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84);
+ tegra_vde_writel(vde, 0x00000010, vde->sxe, 0x08);
+ tegra_vde_writel(vde, 0x00000150, vde->sxe, 0x54);
+ tegra_vde_writel(vde, 0x0000054C, vde->sxe, 0x58);
+ tegra_vde_writel(vde, 0x00000E34, vde->sxe, 0x5C);
+ tegra_vde_writel(vde, 0x063C063C, vde->mce, 0x10);
+ tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS);
+ tegra_vde_writel(vde, 0x0000150D, vde->bsev, BSE_CONFIG);
+ tegra_vde_writel(vde, 0x00000100, vde->bsev, BSE_INT_ENB);
+ tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x98);
+ tegra_vde_writel(vde, 0x00000060, vde->bsev, 0x9C);
+
+ memset(vde->iram + 128, 0, macroblocks_nb / 2);
+
+ tegra_setup_frameidx(vde, dpb_frames, ctx->dpb_frames_nb,
+ ctx->pic_width_in_mbs, ctx->pic_height_in_mbs);
+
+ tegra_vde_setup_iram_tables(vde, dpb_frames,
+ ctx->dpb_frames_nb - 1,
+ ctx->dpb_ref_frames_with_earlier_poc_nb);
+
+ /*
+ * The IRAM mapping is write-combine, ensure that CPU buffers have
+ * been flushed at this point.
+ */
+ wmb();
+
+ tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x8C);
+ tegra_vde_writel(vde, bitstream_data_addr + bitstream_data_size,
+ vde->bsev, 0x54);
+
+ vde->bitstream_data_addr = bitstream_data_addr;
+
+ value = ctx->pic_width_in_mbs << 11 | ctx->pic_height_in_mbs << 3;
+
+ tegra_vde_writel(vde, value, vde->bsev, 0x88);
+
+ err = tegra_vde_wait_bsev(vde, false);
+ if (err)
+ return err;
+
+ err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x800003FC, false);
+ if (err)
+ return err;
+
+ value = 0x01500000;
+ value |= ((vde->iram_lists_addr + 512) >> 2) & 0xFFFF;
+
+ err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true);
+ if (err)
+ return err;
+
+ err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x840F054C, false);
+ if (err)
+ return err;
+
+ err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x80000080, false);
+ if (err)
+ return err;
+
+ value = 0x0E340000 | ((vde->iram_lists_addr >> 2) & 0xFFFF);
+
+ err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true);
+ if (err)
+ return err;
+
+ value = 0x00800005;
+ value |= ctx->pic_width_in_mbs << 11;
+ value |= ctx->pic_height_in_mbs << 3;
+
+ tegra_vde_writel(vde, value, vde->sxe, 0x10);
+
+ value = !ctx->baseline_profile << 17;
+ value |= ctx->level_idc << 13;
+ value |= ctx->log2_max_pic_order_cnt_lsb << 7;
+ value |= ctx->pic_order_cnt_type << 5;
+ value |= ctx->log2_max_frame_num;
+
+ tegra_vde_writel(vde, value, vde->sxe, 0x40);
+
+ value = ctx->pic_init_qp << 25;
+ value |= !!(ctx->deblocking_filter_control_present_flag) << 2;
+ value |= !!ctx->pic_order_present_flag;
+
+ tegra_vde_writel(vde, value, vde->sxe, 0x44);
+
+ value = ctx->chroma_qp_index_offset;
+ value |= ctx->num_ref_idx_l0_active_minus1 << 5;
+ value |= ctx->num_ref_idx_l1_active_minus1 << 10;
+ value |= !!ctx->constrained_intra_pred_flag << 15;
+
+ tegra_vde_writel(vde, value, vde->sxe, 0x48);
+
+ value = 0x0C000000;
+ value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 24;
+
+ tegra_vde_writel(vde, value, vde->sxe, 0x4C);
+
+ value = 0x03800000;
+ value |= bitstream_data_size & GENMASK(19, 15);
+
+ tegra_vde_writel(vde, value, vde->sxe, 0x68);
+
+ tegra_vde_writel(vde, bitstream_data_addr, vde->sxe, 0x6C);
+
+ if (vde->soc->supports_ref_pic_marking)
+ tegra_vde_writel(vde, vde->secure_bo->dma_addr, vde->sxe, 0x7c);
+
+ value = 0x10000005;
+ value |= ctx->pic_width_in_mbs << 11;
+ value |= ctx->pic_height_in_mbs << 3;
+
+ tegra_vde_writel(vde, value, vde->mbe, 0x80);
+
+ value = 0x26800000;
+ value |= ctx->level_idc << 4;
+ value |= !ctx->baseline_profile << 1;
+ value |= !!ctx->direct_8x8_inference_flag;
+
+ tegra_vde_writel(vde, value, vde->mbe, 0x80);
+
+ tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80);
+ tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80);
+ tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80);
+
+ value = 0x20000000;
+ value |= ctx->chroma_qp_index_offset << 8;
+
+ tegra_vde_writel(vde, value, vde->mbe, 0x80);
+
+ err = tegra_vde_setup_mbe_frame_idx(vde,
+ ctx->dpb_frames_nb - 1,
+ ctx->pic_order_cnt_type == 0);
+ if (err) {
+ dev_err(dev, "MBE frames setup failed %d\n", err);
+ return err;
+ }
+
+ tegra_vde_mbe_set_0xa_reg(vde, 0, 0x000009FC);
+ tegra_vde_mbe_set_0xa_reg(vde, 2, 0x61DEAD00);
+ tegra_vde_mbe_set_0xa_reg(vde, 4, 0x62DEAD00);
+ tegra_vde_mbe_set_0xa_reg(vde, 6, 0x63DEAD00);
+ tegra_vde_mbe_set_0xa_reg(vde, 8, dpb_frames[0].aux_addr);
+
+ value = 0xFC000000;
+ value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 2;
+
+ if (!ctx->baseline_profile)
+ value |= !!(dpb_frames[0].flags & FLAG_REFERENCE) << 1;
+
+ tegra_vde_writel(vde, value, vde->mbe, 0x80);
+
+ err = tegra_vde_wait_mbe(vde);
+ if (err) {
+ dev_err(dev, "MBE programming failed %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static void tegra_vde_decode_frame(struct tegra_vde *vde,
+ unsigned int macroblocks_nb)
+{
+ reinit_completion(&vde->decode_completion);
+
+ tegra_vde_writel(vde, 0x00000001, vde->bsev, 0x8C);
+ tegra_vde_writel(vde, 0x20000000 | (macroblocks_nb - 1),
+ vde->sxe, 0x00);
+}
+
+static int tegra_vde_validate_h264_ctx(struct device *dev,
+ struct tegra_vde_h264_decoder_ctx *ctx)
+{
+ if (ctx->dpb_frames_nb == 0 || ctx->dpb_frames_nb > 17) {
+ dev_err(dev, "Bad DPB size %u\n", ctx->dpb_frames_nb);
+ return -EINVAL;
+ }
+
+ if (ctx->level_idc > 15) {
+ dev_err(dev, "Bad level value %u\n", ctx->level_idc);
+ return -EINVAL;
+ }
+
+ if (ctx->pic_init_qp > 52) {
+ dev_err(dev, "Bad pic_init_qp value %u\n", ctx->pic_init_qp);
+ return -EINVAL;
+ }
+
+ if (ctx->log2_max_pic_order_cnt_lsb > 16) {
+ dev_err(dev, "Bad log2_max_pic_order_cnt_lsb value %u\n",
+ ctx->log2_max_pic_order_cnt_lsb);
+ return -EINVAL;
+ }
+
+ if (ctx->log2_max_frame_num > 16) {
+ dev_err(dev, "Bad log2_max_frame_num value %u\n",
+ ctx->log2_max_frame_num);
+ return -EINVAL;
+ }
+
+ if (ctx->chroma_qp_index_offset > 31) {
+ dev_err(dev, "Bad chroma_qp_index_offset value %u\n",
+ ctx->chroma_qp_index_offset);
+ return -EINVAL;
+ }
+
+ if (ctx->pic_order_cnt_type > 2) {
+ dev_err(dev, "Bad pic_order_cnt_type value %u\n",
+ ctx->pic_order_cnt_type);
+ return -EINVAL;
+ }
+
+ if (ctx->num_ref_idx_l0_active_minus1 > 15) {
+ dev_err(dev, "Bad num_ref_idx_l0_active_minus1 value %u\n",
+ ctx->num_ref_idx_l0_active_minus1);
+ return -EINVAL;
+ }
+
+ if (ctx->num_ref_idx_l1_active_minus1 > 15) {
+ dev_err(dev, "Bad num_ref_idx_l1_active_minus1 value %u\n",
+ ctx->num_ref_idx_l1_active_minus1);
+ return -EINVAL;
+ }
+
+ if (!ctx->pic_width_in_mbs || ctx->pic_width_in_mbs > 127) {
+ dev_err(dev, "Bad pic_width_in_mbs value %u\n",
+ ctx->pic_width_in_mbs);
+ return -EINVAL;
+ }
+
+ if (!ctx->pic_height_in_mbs || ctx->pic_height_in_mbs > 127) {
+ dev_err(dev, "Bad pic_height_in_mbs value %u\n",
+ ctx->pic_height_in_mbs);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int tegra_vde_decode_begin(struct tegra_vde *vde,
+ struct tegra_vde_h264_decoder_ctx *ctx,
+ struct tegra_video_frame *dpb_frames,
+ dma_addr_t bitstream_data_addr,
+ size_t bitstream_data_size)
+{
+ struct device *dev = vde->dev;
+ unsigned int macroblocks_nb;
+ int err;
+
+ err = mutex_lock_interruptible(&vde->lock);
+ if (err)
+ return err;
+
+ err = pm_runtime_resume_and_get(dev);
+ if (err < 0)
+ goto unlock;
+
+ /*
+ * We rely on the VDE registers reset value, otherwise VDE
+ * causes bus lockup.
+ */
+ err = reset_control_assert(vde->rst_mc);
+ if (err) {
+ dev_err(dev, "DEC start: Failed to assert MC reset: %d\n",
+ err);
+ goto put_runtime_pm;
+ }
+
+ err = reset_control_reset(vde->rst);
+ if (err) {
+ dev_err(dev, "DEC start: Failed to reset HW: %d\n", err);
+ goto put_runtime_pm;
+ }
+
+ err = reset_control_deassert(vde->rst_mc);
+ if (err) {
+ dev_err(dev, "DEC start: Failed to deassert MC reset: %d\n",
+ err);
+ goto put_runtime_pm;
+ }
+
+ macroblocks_nb = ctx->pic_width_in_mbs * ctx->pic_height_in_mbs;
+
+ err = tegra_vde_setup_hw_context(vde, ctx, dpb_frames,
+ bitstream_data_addr,
+ bitstream_data_size,
+ macroblocks_nb);
+ if (err)
+ goto put_runtime_pm;
+
+ tegra_vde_decode_frame(vde, macroblocks_nb);
+
+ return 0;
+
+put_runtime_pm:
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+
+unlock:
+ mutex_unlock(&vde->lock);
+
+ return err;
+}
+
+static void tegra_vde_decode_abort(struct tegra_vde *vde)
+{
+ struct device *dev = vde->dev;
+ int err;
+
+ /*
+ * At first reset memory client to avoid resetting VDE HW in the
+ * middle of DMA which could result into memory corruption or hang
+ * the whole system.
+ */
+ err = reset_control_assert(vde->rst_mc);
+ if (err)
+ dev_err(dev, "DEC end: Failed to assert MC reset: %d\n", err);
+
+ err = reset_control_assert(vde->rst);
+ if (err)
+ dev_err(dev, "DEC end: Failed to assert HW reset: %d\n", err);
+
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+
+ mutex_unlock(&vde->lock);
+}
+
+static int tegra_vde_decode_end(struct tegra_vde *vde)
+{
+ unsigned int read_bytes, macroblocks_nb;
+ struct device *dev = vde->dev;
+ dma_addr_t bsev_ptr;
+ long timeout;
+ int ret;
+
+ timeout = wait_for_completion_interruptible_timeout(
+ &vde->decode_completion, msecs_to_jiffies(1000));
+ if (timeout == 0) {
+ bsev_ptr = tegra_vde_readl(vde, vde->bsev, 0x10);
+ macroblocks_nb = tegra_vde_readl(vde, vde->sxe, 0xC8) & 0x1FFF;
+ read_bytes = bsev_ptr ? bsev_ptr - vde->bitstream_data_addr : 0;
+
+ dev_err(dev, "Decoding failed: read 0x%X bytes, %u macroblocks parsed\n",
+ read_bytes, macroblocks_nb);
+
+ ret = -EIO;
+ } else if (timeout < 0) {
+ ret = timeout;
+ } else {
+ ret = 0;
+ }
+
+ tegra_vde_decode_abort(vde);
+
+ return ret;
+}
+
+static struct vb2_buffer *get_ref_buf(struct tegra_ctx *ctx,
+ struct vb2_v4l2_buffer *dst,
+ unsigned int dpb_idx)
+{
+ const struct v4l2_h264_dpb_entry *dpb = ctx->h264.decode_params->dpb;
+ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q;
+ int buf_idx = -1;
+
+ if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
+ buf_idx = vb2_find_timestamp(cap_q,
+ dpb[dpb_idx].reference_ts, 0);
+
+ /*
+ * If a DPB entry is unused or invalid, address of current destination
+ * buffer is returned.
+ */
+ if (buf_idx < 0)
+ return &dst->vb2_buf;
+
+ return vb2_get_buffer(cap_q, buf_idx);
+}
+
+static int tegra_vde_validate_vb_size(struct tegra_ctx *ctx,
+ struct vb2_buffer *vb,
+ unsigned int plane_id,
+ size_t min_size)
+{
+ u64 offset = vb->planes[plane_id].data_offset;
+ struct device *dev = ctx->vde->dev;
+
+ if (offset + min_size > vb2_plane_size(vb, plane_id)) {
+ dev_err(dev, "Too small plane[%u] size %lu @0x%llX, should be at least %zu\n",
+ plane_id, vb2_plane_size(vb, plane_id), offset, min_size);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int tegra_vde_h264_setup_frame(struct tegra_ctx *ctx,
+ struct tegra_vde_h264_decoder_ctx *h264,
+ struct v4l2_h264_reflist_builder *b,
+ struct vb2_buffer *vb,
+ unsigned int ref_id,
+ unsigned int id)
+{
+ struct v4l2_pix_format_mplane *pixfmt = &ctx->decoded_fmt.fmt.pix_mp;
+ struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb);
+ struct tegra_ctx_h264 *h = &ctx->h264;
+ struct tegra_vde *vde = ctx->vde;
+ struct device *dev = vde->dev;
+ unsigned int cstride, lstride;
+ unsigned int flags = 0;
+ size_t lsize, csize;
+ int err, frame_num;
+
+ lsize = h264->pic_width_in_mbs * 16 * h264->pic_height_in_mbs * 16;
+ csize = h264->pic_width_in_mbs * 8 * h264->pic_height_in_mbs * 8;
+ lstride = pixfmt->plane_fmt[0].bytesperline;
+ cstride = pixfmt->plane_fmt[1].bytesperline;
+
+ err = tegra_vde_validate_vb_size(ctx, vb, 0, lsize);
+ if (err)
+ return err;
+
+ err = tegra_vde_validate_vb_size(ctx, vb, 1, csize);
+ if (err)
+ return err;
+
+ err = tegra_vde_validate_vb_size(ctx, vb, 2, csize);
+ if (err)
+ return err;
+
+ if (!tb->aux || tb->aux->size < csize) {
+ dev_err(dev, "Too small aux size %zd, should be at least %zu\n",
+ tb->aux ? tb->aux->size : -1, csize);
+ return -EINVAL;
+ }
+
+ if (id == 0) {
+ frame_num = h->decode_params->frame_num;
+
+ if (h->decode_params->nal_ref_idc)
+ flags |= FLAG_REFERENCE;
+ } else {
+ frame_num = b->refs[ref_id].frame_num;
+ }
+
+ if (tb->b_frame)
+ flags |= FLAG_B_FRAME;
+
+ vde->frames[id].flags = flags;
+ vde->frames[id].y_addr = tb->dma_addr[0];
+ vde->frames[id].cb_addr = tb->dma_addr[1];
+ vde->frames[id].cr_addr = tb->dma_addr[2];
+ vde->frames[id].aux_addr = tb->aux->dma_addr;
+ vde->frames[id].frame_num = frame_num & 0x7fffff;
+ vde->frames[id].luma_atoms_pitch = lstride / VDE_ATOM;
+ vde->frames[id].chroma_atoms_pitch = cstride / VDE_ATOM;
+
+ return 0;
+}
+
+static int tegra_vde_h264_setup_frames(struct tegra_ctx *ctx,
+ struct tegra_vde_h264_decoder_ctx *h264)
+{
+ struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
+ struct vb2_v4l2_buffer *dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
+ const struct v4l2_h264_dpb_entry *dpb = ctx->h264.decode_params->dpb;
+ struct tegra_m2m_buffer *tb = vb_to_tegra_buf(&dst->vb2_buf);
+ struct tegra_ctx_h264 *h = &ctx->h264;
+ struct v4l2_h264_reflist_builder b;
+ struct h264_reflists reflists;
+ struct vb2_buffer *ref;
+ unsigned int i;
+ u8 *dpb_id;
+ int err;
+
+ /*
+ * Tegra hardware requires information about frame's type, assuming
+ * that frame consists of the same type slices. Userspace must tag
+ * frame's type appropriately.
+ *
+ * Decoding of a non-uniform frames isn't supported by hardware and
+ * require software preprocessing that we don't implement. Decoding
+ * is expected to fail in this case. Such video streams are rare in
+ * practice, so not a big deal.
+ *
+ * If userspace doesn't tell us frame's type, then we will try decode
+ * as-is.
+ */
+ v4l2_m2m_buf_copy_metadata(src, dst, true);
+
+ if (h->decode_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BFRAME)
+ tb->b_frame = true;
+ else
+ tb->b_frame = false;
+
+ err = tegra_vde_h264_setup_frame(ctx, h264, NULL, &dst->vb2_buf, 0,
+ h264->dpb_frames_nb++);
+ if (err)
+ return err;
+
+ if (!(h->decode_params->flags & (V4L2_H264_DECODE_PARAM_FLAG_PFRAME |
+ V4L2_H264_DECODE_PARAM_FLAG_BFRAME)))
+ return 0;
+
+ v4l2_h264_init_reflist_builder(&b, h->decode_params, h->sps, dpb);
+
+ if (h->decode_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BFRAME) {
+ v4l2_h264_build_b_ref_lists(&b, reflists.b0, reflists.b1);
+ dpb_id = reflists.b0;
+ } else {
+ v4l2_h264_build_p_ref_list(&b, reflists.p);
+ dpb_id = reflists.p;
+ }
+
+ for (i = 0; i < b.num_valid; i++) {
+ ref = get_ref_buf(ctx, dst, dpb_id[i]);
+
+ err = tegra_vde_h264_setup_frame(ctx, h264, &b, ref, dpb_id[i],
+ h264->dpb_frames_nb++);
+ if (err)
+ return err;
+
+ if (b.refs[dpb_id[i]].pic_order_count < b.cur_pic_order_count)
+ h264->dpb_ref_frames_with_earlier_poc_nb++;
+ }
+
+ return 0;
+}
+
+static unsigned int to_tegra_vde_h264_level_idc(unsigned int level_idc)
+{
+ switch (level_idc) {
+ case 11:
+ return 2;
+ case 12:
+ return 3;
+ case 13:
+ return 4;
+ case 20:
+ return 5;
+ case 21:
+ return 6;
+ case 22:
+ return 7;
+ case 30:
+ return 8;
+ case 31:
+ return 9;
+ case 32:
+ return 10;
+ case 40:
+ return 11;
+ case 41:
+ return 12;
+ case 42:
+ return 13;
+ case 50:
+ return 14;
+ default:
+ break;
+ }
+
+ return 15;
+}
+
+static int tegra_vde_h264_setup_context(struct tegra_ctx *ctx,
+ struct tegra_vde_h264_decoder_ctx *h264)
+{
+ struct tegra_ctx_h264 *h = &ctx->h264;
+ struct tegra_vde *vde = ctx->vde;
+ struct device *dev = vde->dev;
+ int err;
+
+ memset(h264, 0, sizeof(*h264));
+ memset(vde->frames, 0, sizeof(vde->frames));
+
+ tegra_vde_prepare_control_data(ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS);
+ tegra_vde_prepare_control_data(ctx, V4L2_CID_STATELESS_H264_SPS);
+ tegra_vde_prepare_control_data(ctx, V4L2_CID_STATELESS_H264_PPS);
+
+ /* CABAC unsupported by hardware, requires software preprocessing */
+ if (h->pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE)
+ return -EOPNOTSUPP;
+
+ if (h->sps->profile_idc == 66)
+ h264->baseline_profile = 1;
+
+ if (h->sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE)
+ h264->direct_8x8_inference_flag = 1;
+
+ if (h->pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED)
+ h264->constrained_intra_pred_flag = 1;
+
+ if (h->pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT)
+ h264->deblocking_filter_control_present_flag = 1;
+
+ if (h->pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT)
+ h264->pic_order_present_flag = 1;
+
+ h264->level_idc = to_tegra_vde_h264_level_idc(h->sps->level_idc);
+ h264->log2_max_pic_order_cnt_lsb = h->sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
+ h264->log2_max_frame_num = h->sps->log2_max_frame_num_minus4 + 4;
+ h264->pic_order_cnt_type = h->sps->pic_order_cnt_type;
+ h264->pic_width_in_mbs = h->sps->pic_width_in_mbs_minus1 + 1;
+ h264->pic_height_in_mbs = h->sps->pic_height_in_map_units_minus1 + 1;
+
+ h264->num_ref_idx_l0_active_minus1 = h->pps->num_ref_idx_l0_default_active_minus1;
+ h264->num_ref_idx_l1_active_minus1 = h->pps->num_ref_idx_l1_default_active_minus1;
+ h264->chroma_qp_index_offset = h->pps->chroma_qp_index_offset & 0x1f;
+ h264->pic_init_qp = h->pps->pic_init_qp_minus26 + 26;
+
+ err = tegra_vde_h264_setup_frames(ctx, h264);
+ if (err)
+ return err;
+
+ err = tegra_vde_validate_h264_ctx(dev, h264);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+int tegra_vde_h264_decode_run(struct tegra_ctx *ctx)
+{
+ struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
+ struct tegra_m2m_buffer *bitstream = vb_to_tegra_buf(&src->vb2_buf);
+ size_t bitstream_size = vb2_get_plane_payload(&src->vb2_buf, 0);
+ struct tegra_vde_h264_decoder_ctx h264;
+ struct tegra_vde *vde = ctx->vde;
+ int err;
+
+ err = tegra_vde_h264_setup_context(ctx, &h264);
+ if (err)
+ return err;
+
+ err = tegra_vde_decode_begin(vde, &h264, vde->frames,
+ bitstream->dma_addr[0],
+ bitstream_size);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+int tegra_vde_h264_decode_wait(struct tegra_ctx *ctx)
+{
+ return tegra_vde_decode_end(ctx->vde);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NVIDIA Tegra Video decoder driver
+ *
+ * Copyright (C) 2016-2019 GRATE-DRIVER project
+ */
+
+#include <linux/iommu.h>
+#include <linux/iova.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
+#include <asm/dma-iommu.h>
+#endif
+
+#include "vde.h"
+
+int tegra_vde_iommu_map(struct tegra_vde *vde,
+ struct sg_table *sgt,
+ struct iova **iovap,
+ size_t size)
+{
+ struct iova *iova;
+ unsigned long shift;
+ unsigned long end;
+ dma_addr_t addr;
+
+ end = vde->domain->geometry.aperture_end;
+ size = iova_align(&vde->iova, size);
+ shift = iova_shift(&vde->iova);
+
+ iova = alloc_iova(&vde->iova, size >> shift, end >> shift, true);
+ if (!iova)
+ return -ENOMEM;
+
+ addr = iova_dma_addr(&vde->iova, iova);
+
+ size = iommu_map_sgtable(vde->domain, addr, sgt,
+ IOMMU_READ | IOMMU_WRITE);
+ if (!size) {
+ __free_iova(&vde->iova, iova);
+ return -ENXIO;
+ }
+
+ *iovap = iova;
+
+ return 0;
+}
+
+void tegra_vde_iommu_unmap(struct tegra_vde *vde, struct iova *iova)
+{
+ unsigned long shift = iova_shift(&vde->iova);
+ unsigned long size = iova_size(iova) << shift;
+ dma_addr_t addr = iova_dma_addr(&vde->iova, iova);
+
+ iommu_unmap(vde->domain, addr, size);
+ __free_iova(&vde->iova, iova);
+}
+
+int tegra_vde_iommu_init(struct tegra_vde *vde)
+{
+ struct device *dev = vde->dev;
+ struct iova *iova;
+ unsigned long order;
+ unsigned long shift;
+ int err;
+
+ vde->group = iommu_group_get(dev);
+ if (!vde->group)
+ return 0;
+
+#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
+ if (dev->archdata.mapping) {
+ struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
+
+ arm_iommu_detach_device(dev);
+ arm_iommu_release_mapping(mapping);
+ }
+#endif
+ vde->domain = iommu_domain_alloc(&platform_bus_type);
+ if (!vde->domain) {
+ err = -ENOMEM;
+ goto put_group;
+ }
+
+ err = iova_cache_get();
+ if (err)
+ goto free_domain;
+
+ order = __ffs(vde->domain->pgsize_bitmap);
+ init_iova_domain(&vde->iova, 1UL << order, 0);
+
+ err = iommu_attach_group(vde->domain, vde->group);
+ if (err)
+ goto put_iova;
+
+ /*
+ * We're using some static addresses that are not accessible by VDE
+ * to trap invalid memory accesses.
+ */
+ shift = iova_shift(&vde->iova);
+ iova = reserve_iova(&vde->iova, 0x60000000 >> shift,
+ 0x70000000 >> shift);
+ if (!iova) {
+ err = -ENOMEM;
+ goto detach_group;
+ }
+
+ vde->iova_resv_static_addresses = iova;
+
+ /*
+ * BSEV's end-address wraps around due to integer overflow during
+ * of hardware context preparation if IOVA is allocated at the end
+ * of address space and VDE can't handle that. Hence simply reserve
+ * the last page to avoid the problem.
+ */
+ iova = reserve_iova(&vde->iova, 0xffffffff >> shift,
+ (0xffffffff >> shift) + 1);
+ if (!iova) {
+ err = -ENOMEM;
+ goto unreserve_iova;
+ }
+
+ vde->iova_resv_last_page = iova;
+
+ return 0;
+
+unreserve_iova:
+ __free_iova(&vde->iova, vde->iova_resv_static_addresses);
+detach_group:
+ iommu_detach_group(vde->domain, vde->group);
+put_iova:
+ put_iova_domain(&vde->iova);
+ iova_cache_put();
+free_domain:
+ iommu_domain_free(vde->domain);
+put_group:
+ iommu_group_put(vde->group);
+
+ return err;
+}
+
+void tegra_vde_iommu_deinit(struct tegra_vde *vde)
+{
+ if (vde->domain) {
+ __free_iova(&vde->iova, vde->iova_resv_last_page);
+ __free_iova(&vde->iova, vde->iova_resv_static_addresses);
+ iommu_detach_group(vde->domain, vde->group);
+ put_iova_domain(&vde->iova);
+ iova_cache_put();
+ iommu_domain_free(vde->domain);
+ iommu_group_put(vde->group);
+
+ vde->domain = NULL;
+ }
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM tegra_vde
+
+#if !defined(TEGRA_VDE_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
+#define TEGRA_VDE_TRACE_H
+
+#include <linux/tracepoint.h>
+
+#include "vde.h"
+
+DECLARE_EVENT_CLASS(register_access,
+ TP_PROTO(struct tegra_vde *vde, void __iomem *base,
+ u32 offset, u32 value),
+ TP_ARGS(vde, base, offset, value),
+ TP_STRUCT__entry(
+ __string(hw_name, tegra_vde_reg_base_name(vde, base))
+ __field(u32, offset)
+ __field(u32, value)
+ ),
+ TP_fast_assign(
+ __assign_str(hw_name, tegra_vde_reg_base_name(vde, base));
+ __entry->offset = offset;
+ __entry->value = value;
+ ),
+ TP_printk("%s:0x%03x 0x%08x", __get_str(hw_name), __entry->offset,
+ __entry->value)
+);
+
+DEFINE_EVENT(register_access, vde_writel,
+ TP_PROTO(struct tegra_vde *vde, void __iomem *base,
+ u32 offset, u32 value),
+ TP_ARGS(vde, base, offset, value));
+DEFINE_EVENT(register_access, vde_readl,
+ TP_PROTO(struct tegra_vde *vde, void __iomem *base,
+ u32 offset, u32 value),
+ TP_ARGS(vde, base, offset, value));
+
+TRACE_EVENT(vde_setup_iram_entry,
+ TP_PROTO(unsigned int table, unsigned int row, u32 value, u32 aux_addr),
+ TP_ARGS(table, row, value, aux_addr),
+ TP_STRUCT__entry(
+ __field(unsigned int, table)
+ __field(unsigned int, row)
+ __field(u32, value)
+ __field(u32, aux_addr)
+ ),
+ TP_fast_assign(
+ __entry->table = table;
+ __entry->row = row;
+ __entry->value = value;
+ __entry->aux_addr = aux_addr;
+ ),
+ TP_printk("[%u][%u] = { 0x%08x (flags = \"%s\", frame_num = %u); 0x%08x }",
+ __entry->table, __entry->row, __entry->value,
+ __print_flags(__entry->value, " ", { (1 << 25), "B" }),
+ __entry->value & 0x7FFFFF, __entry->aux_addr)
+);
+
+TRACE_EVENT(vde_ref_l0,
+ TP_PROTO(unsigned int frame_num),
+ TP_ARGS(frame_num),
+ TP_STRUCT__entry(
+ __field(unsigned int, frame_num)
+ ),
+ TP_fast_assign(
+ __entry->frame_num = frame_num;
+ ),
+ TP_printk("REF L0: DPB: Frame 0: frame_num = %u", __entry->frame_num)
+);
+
+TRACE_EVENT(vde_ref_l1,
+ TP_PROTO(unsigned int with_later_poc_nb,
+ unsigned int with_earlier_poc_nb),
+ TP_ARGS(with_later_poc_nb, with_earlier_poc_nb),
+ TP_STRUCT__entry(
+ __field(unsigned int, with_later_poc_nb)
+ __field(unsigned int, with_earlier_poc_nb)
+ ),
+ TP_fast_assign(
+ __entry->with_later_poc_nb = with_later_poc_nb;
+ __entry->with_earlier_poc_nb = with_earlier_poc_nb;
+ ),
+ TP_printk("REF L1: with_later_poc_nb %u, with_earlier_poc_nb %u",
+ __entry->with_later_poc_nb, __entry->with_earlier_poc_nb)
+);
+
+#endif /* TEGRA_VDE_TRACE_H */
+
+/* This part must be outside protection */
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH ../../drivers/media/platform/nvidia/tegra-vde
+#define TRACE_INCLUDE_FILE trace
+#include <trace/define_trace.h>
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NVIDIA Tegra Video decoder driver
+ *
+ * Copyright (C) 2019-2022 Dmitry Osipenko <digetx@gmail.com>
+ *
+ * Based on Cedrus driver by Bootlin.
+ * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
+ * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
+ *
+ * Based on Rockchip driver by Collabora.
+ * Copyright (C) 2019 Boris Brezillon <boris.brezillon@collabora.com>
+ */
+
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include "vde.h"
+
+static const struct v4l2_ctrl_config ctrl_cfgs[] = {
+ { .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, },
+ { .id = V4L2_CID_STATELESS_H264_SPS, },
+ { .id = V4L2_CID_STATELESS_H264_PPS, },
+ {
+ .id = V4L2_CID_STATELESS_H264_DECODE_MODE,
+ .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
+ .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
+ .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
+ },
+ {
+ .id = V4L2_CID_STATELESS_H264_START_CODE,
+ .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
+ .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
+ .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
+ },
+ {
+ .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
+ .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
+ .max = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
+ .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
+ },
+ {
+ .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL,
+ .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
+ .max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
+ },
+};
+
+static inline struct tegra_ctx *fh_to_tegra_ctx(struct v4l2_fh *fh)
+{
+ return container_of(fh, struct tegra_ctx, fh);
+}
+
+static void tegra_set_control_data(struct tegra_ctx *ctx, void *data, u32 id)
+{
+ switch (id) {
+ case V4L2_CID_STATELESS_H264_DECODE_PARAMS:
+ ctx->h264.decode_params = data;
+ break;
+ case V4L2_CID_STATELESS_H264_SPS:
+ ctx->h264.sps = data;
+ break;
+ case V4L2_CID_STATELESS_H264_PPS:
+ ctx->h264.pps = data;
+ break;
+ }
+}
+
+void tegra_vde_prepare_control_data(struct tegra_ctx *ctx, u32 id)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(ctrl_cfgs); i++) {
+ if (ctx->ctrls[i]->id == id) {
+ tegra_set_control_data(ctx, ctx->ctrls[i]->p_cur.p, id);
+ return;
+ }
+ }
+
+ tegra_set_control_data(ctx, NULL, id);
+}
+
+static int tegra_queue_setup(struct vb2_queue *vq,
+ unsigned int *nbufs,
+ unsigned int *num_planes,
+ unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ struct tegra_ctx *ctx = vb2_get_drv_priv(vq);
+ struct v4l2_format *f;
+ unsigned int i;
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type))
+ f = &ctx->coded_fmt;
+ else
+ f = &ctx->decoded_fmt;
+
+ if (*num_planes) {
+ if (*num_planes != f->fmt.pix_mp.num_planes)
+ return -EINVAL;
+
+ for (i = 0; i < f->fmt.pix_mp.num_planes; i++) {
+ if (sizes[i] < f->fmt.pix_mp.plane_fmt[i].sizeimage)
+ return -EINVAL;
+ }
+ } else {
+ *num_planes = f->fmt.pix_mp.num_planes;
+
+ for (i = 0; i < f->fmt.pix_mp.num_planes; i++)
+ sizes[i] = f->fmt.pix_mp.plane_fmt[i].sizeimage;
+ }
+
+ return 0;
+}
+
+static int tegra_buf_out_validate(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+
+ vbuf->field = V4L2_FIELD_NONE;
+ return 0;
+}
+
+static void __tegra_buf_cleanup(struct vb2_buffer *vb, unsigned int i)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct tegra_ctx *ctx = vb2_get_drv_priv(vq);
+ struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb);
+
+ while (i--) {
+ if (tb->a[i]) {
+ tegra_vde_dmabuf_cache_unmap(ctx->vde, tb->a[i], true);
+ tb->a[i] = NULL;
+ }
+
+ if (tb->iova[i]) {
+ tegra_vde_iommu_unmap(ctx->vde, tb->iova[i]);
+ tb->iova[i] = NULL;
+ }
+ }
+
+ if (tb->aux) {
+ tegra_vde_free_bo(tb->aux);
+ tb->aux = NULL;
+ }
+}
+
+static int tegra_buf_init(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct tegra_ctx *ctx = vb2_get_drv_priv(vq);
+ struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb);
+ struct tegra_vde *vde = ctx->vde;
+ enum dma_data_direction dma_dir;
+ struct sg_table *sgt;
+ unsigned int i;
+ int err;
+
+ if (V4L2_TYPE_IS_CAPTURE(vq->type) && vb->num_planes > 1) {
+ /*
+ * Tegra decoder writes auxiliary data for I/P frames.
+ * This data is needed for decoding of B frames.
+ */
+ err = tegra_vde_alloc_bo(vde, &tb->aux, DMA_FROM_DEVICE,
+ vb2_plane_size(vb, 1));
+ if (err)
+ return err;
+ }
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type))
+ dma_dir = DMA_TO_DEVICE;
+ else
+ dma_dir = DMA_FROM_DEVICE;
+
+ for (i = 0; i < vb->num_planes; i++) {
+ if (vq->memory == VB2_MEMORY_DMABUF) {
+ get_dma_buf(vb->planes[i].dbuf);
+
+ err = tegra_vde_dmabuf_cache_map(vde, vb->planes[i].dbuf,
+ dma_dir, &tb->a[i],
+ &tb->dma_base[i]);
+ if (err) {
+ dma_buf_put(vb->planes[i].dbuf);
+ goto cleanup;
+ }
+
+ continue;
+ }
+
+ if (vde->domain) {
+ sgt = vb2_dma_sg_plane_desc(vb, i);
+
+ err = tegra_vde_iommu_map(vde, sgt, &tb->iova[i],
+ vb2_plane_size(vb, i));
+ if (err)
+ goto cleanup;
+
+ tb->dma_base[i] = iova_dma_addr(&vde->iova, tb->iova[i]);
+ } else {
+ tb->dma_base[i] = vb2_dma_contig_plane_dma_addr(vb, i);
+ }
+ }
+
+ return 0;
+
+cleanup:
+ __tegra_buf_cleanup(vb, i);
+
+ return err;
+}
+
+static void tegra_buf_cleanup(struct vb2_buffer *vb)
+{
+ __tegra_buf_cleanup(vb, vb->num_planes);
+}
+
+static int tegra_buf_prepare(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct tegra_ctx *ctx = vb2_get_drv_priv(vq);
+ struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb);
+ size_t hw_align, hw_size, hw_payload, size, offset;
+ struct v4l2_pix_format_mplane *pixfmt;
+ unsigned int i;
+ void *vb_data;
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
+ hw_align = BSEV_ALIGN;
+ pixfmt = &ctx->coded_fmt.fmt.pix_mp;
+ } else {
+ hw_align = FRAMEID_ALIGN;
+ pixfmt = &ctx->decoded_fmt.fmt.pix_mp;
+ }
+
+ for (i = 0; i < vb->num_planes; i++) {
+ offset = vb->planes[i].data_offset;
+
+ if (offset & (hw_align - 1))
+ return -EINVAL;
+
+ if (V4L2_TYPE_IS_CAPTURE(vq->type)) {
+ size = pixfmt->plane_fmt[i].sizeimage;
+ hw_payload = ALIGN(size, VDE_ATOM);
+ } else {
+ size = vb2_get_plane_payload(vb, i) - offset;
+ hw_payload = ALIGN(size + VDE_ATOM, SXE_BUFFER);
+ }
+
+ hw_size = offset + hw_payload;
+
+ if (vb2_plane_size(vb, i) < hw_size)
+ return -EINVAL;
+
+ vb2_set_plane_payload(vb, i, hw_payload);
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
+ vb_data = vb2_plane_vaddr(vb, i);
+
+ /*
+ * Hardware requires zero-padding of coded data.
+ * Otherwise it will fail to parse the trailing
+ * data and abort the decoding.
+ */
+ if (vb_data)
+ memset(vb_data + offset + size, 0,
+ hw_size - offset - size);
+ }
+
+ tb->dma_addr[i] = tb->dma_base[i] + offset;
+ }
+
+ switch (pixfmt->pixelformat) {
+ case V4L2_PIX_FMT_YVU420M:
+ swap(tb->dma_addr[1], tb->dma_addr[2]);
+ break;
+ }
+
+ return 0;
+}
+
+static void tegra_buf_queue(struct vb2_buffer *vb)
+{
+ struct tegra_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+
+ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
+}
+
+static void tegra_buf_request_complete(struct vb2_buffer *vb)
+{
+ struct tegra_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+
+ v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->hdl);
+}
+
+static int tegra_start_streaming(struct vb2_queue *vq, unsigned int count)
+{
+ return 0;
+}
+
+static void tegra_stop_streaming(struct vb2_queue *vq)
+{
+ struct tegra_ctx *ctx = vb2_get_drv_priv(vq);
+
+ while (true) {
+ struct vb2_v4l2_buffer *vbuf;
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type))
+ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+ else
+ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+
+ if (!vbuf)
+ break;
+
+ v4l2_ctrl_request_complete(vbuf->vb2_buf.req_obj.req, &ctx->hdl);
+ v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
+ }
+}
+
+static const struct vb2_ops tegra_qops = {
+ .queue_setup = tegra_queue_setup,
+ .buf_init = tegra_buf_init,
+ .buf_cleanup = tegra_buf_cleanup,
+ .buf_prepare = tegra_buf_prepare,
+ .buf_queue = tegra_buf_queue,
+ .buf_out_validate = tegra_buf_out_validate,
+ .buf_request_complete = tegra_buf_request_complete,
+ .start_streaming = tegra_start_streaming,
+ .stop_streaming = tegra_stop_streaming,
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+};
+
+static int tegra_queue_init(void *priv,
+ struct vb2_queue *src_vq,
+ struct vb2_queue *dst_vq)
+{
+ struct tegra_ctx *ctx = priv;
+ struct tegra_vde *vde = ctx->vde;
+ const struct vb2_mem_ops *mem_ops;
+ unsigned long dma_attrs;
+ int err;
+
+ /*
+ * TODO: Switch to use of vb2_dma_contig_memops uniformly once we
+ * will add IOMMU_DOMAIN support for video decoder to tegra-smmu
+ * driver. For now we need to stick with SG ops in order to be able
+ * to get SGT table easily. This is suboptimal since SG mappings are
+ * wasting CPU cache and we don't need that caching.
+ */
+ if (vde->domain)
+ mem_ops = &vb2_dma_sg_memops;
+ else
+ mem_ops = &vb2_dma_contig_memops;
+
+ dma_attrs = DMA_ATTR_WRITE_COMBINE;
+
+ src_vq->buf_struct_size = sizeof(struct tegra_m2m_buffer);
+ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+ src_vq->io_modes = VB2_DMABUF | VB2_MMAP;
+ src_vq->supports_requests = true;
+ src_vq->requires_requests = true;
+ src_vq->lock = &vde->v4l2_lock;
+ src_vq->dma_attrs = dma_attrs;
+ src_vq->mem_ops = mem_ops;
+ src_vq->ops = &tegra_qops;
+ src_vq->drv_priv = ctx;
+ src_vq->dev = vde->dev;
+
+ err = vb2_queue_init(src_vq);
+ if (err) {
+ v4l2_err(&vde->v4l2_dev,
+ "failed to initialize src queue: %d\n", err);
+ return err;
+ }
+
+ /*
+ * We may need to zero the end of bitstream in kernel if userspace
+ * doesn't do that, hence kmap is needed for the coded data. It's not
+ * needed for framebuffers.
+ */
+ dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
+
+ dst_vq->buf_struct_size = sizeof(struct tegra_m2m_buffer);
+ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+ dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
+ dst_vq->lock = &vde->v4l2_lock;
+ dst_vq->dma_attrs = dma_attrs;
+ dst_vq->mem_ops = mem_ops;
+ dst_vq->ops = &tegra_qops;
+ dst_vq->drv_priv = ctx;
+ dst_vq->dev = vde->dev;
+
+ err = vb2_queue_init(dst_vq);
+ if (err) {
+ v4l2_err(&vde->v4l2_dev,
+ "failed to initialize dst queue: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static void tegra_reset_fmt(struct tegra_ctx *ctx, struct v4l2_format *f,
+ u32 fourcc)
+{
+ memset(f, 0, sizeof(*f));
+ f->fmt.pix_mp.pixelformat = fourcc;
+ f->fmt.pix_mp.field = V4L2_FIELD_NONE;
+ f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT;
+ f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+ f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709;
+ f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
+}
+
+static void tegra_reset_coded_fmt(struct tegra_ctx *ctx)
+{
+ const struct tegra_vde_soc *soc = ctx->vde->soc;
+ struct v4l2_format *f = &ctx->coded_fmt;
+
+ ctx->coded_fmt_desc = &soc->coded_fmts[0];
+ tegra_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc);
+
+ f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+ f->fmt.pix_mp.width = ctx->coded_fmt_desc->frmsize.min_width;
+ f->fmt.pix_mp.height = ctx->coded_fmt_desc->frmsize.min_height;
+}
+
+static void tegra_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
+ u32 pixelformat, u32 width, u32 height)
+{
+ const struct v4l2_format_info *info = v4l2_format_info(pixelformat);
+ struct v4l2_plane_pix_format *plane;
+ unsigned int i;
+
+ switch (pixelformat) {
+ case V4L2_PIX_FMT_YUV420M:
+ case V4L2_PIX_FMT_YVU420M:
+ pixfmt->width = width;
+ pixfmt->height = height;
+ pixfmt->pixelformat = pixelformat;
+ pixfmt->num_planes = info->mem_planes;
+
+ for (i = 0; i < pixfmt->num_planes; i++) {
+ unsigned int hdiv = (i == 0) ? 1 : 2;
+ unsigned int vdiv = (i == 0) ? 1 : 2;
+
+ /*
+ * VDE is connected to Graphics Memory using 128bit port,
+ * all memory accesses are made using 16B atoms.
+ *
+ * V4L requires Cb/Cr strides to be exactly half of the
+ * Y stride, hence we're aligning Y to 16B x 2.
+ */
+ plane = &pixfmt->plane_fmt[i];
+ plane->bytesperline = ALIGN(width, VDE_ATOM * 2) / hdiv;
+ plane->sizeimage = plane->bytesperline * height / vdiv;
+ }
+
+ break;
+ }
+}
+
+static void tegra_reset_decoded_fmt(struct tegra_ctx *ctx)
+{
+ struct v4l2_format *f = &ctx->decoded_fmt;
+
+ tegra_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
+ f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+ tegra_fill_pixfmt_mp(&f->fmt.pix_mp,
+ ctx->coded_fmt_desc->decoded_fmts[0],
+ ctx->coded_fmt.fmt.pix_mp.width,
+ ctx->coded_fmt.fmt.pix_mp.height);
+}
+
+static void tegra_job_finish(struct tegra_ctx *ctx,
+ enum vb2_buffer_state result)
+{
+ v4l2_m2m_buf_done_and_job_finish(ctx->vde->m2m, ctx->fh.m2m_ctx,
+ result);
+}
+
+static void tegra_decode_complete(struct work_struct *work)
+{
+ struct tegra_ctx *ctx = container_of(work, struct tegra_ctx, work);
+ int err;
+
+ err = ctx->coded_fmt_desc->decode_wait(ctx);
+ if (err)
+ tegra_job_finish(ctx, VB2_BUF_STATE_ERROR);
+ else
+ tegra_job_finish(ctx, VB2_BUF_STATE_DONE);
+}
+
+static int tegra_querycap(struct file *file, void *priv,
+ struct v4l2_capability *cap)
+{
+ strscpy(cap->bus_info, "platform:tegra-vde", sizeof(cap->bus_info));
+ strscpy(cap->driver, "tegra-vde", sizeof(cap->driver));
+ strscpy(cap->card, "tegra-vde", sizeof(cap->card));
+
+ return 0;
+}
+
+static int tegra_enum_decoded_fmt(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
+
+ if (WARN_ON(!ctx->coded_fmt_desc))
+ return -EINVAL;
+
+ if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts)
+ return -EINVAL;
+
+ f->pixelformat = ctx->coded_fmt_desc->decoded_fmts[f->index];
+
+ return 0;
+}
+
+static int tegra_g_decoded_fmt(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
+
+ *f = ctx->decoded_fmt;
+ return 0;
+}
+
+static int tegra_try_decoded_fmt(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
+ struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
+ const struct tegra_coded_fmt_desc *coded_desc;
+ unsigned int i;
+
+ /*
+ * The codec context should point to a coded format desc, if the format
+ * on the coded end has not been set yet, it should point to the
+ * default value.
+ */
+ coded_desc = ctx->coded_fmt_desc;
+ if (WARN_ON(!coded_desc))
+ return -EINVAL;
+
+ if (!coded_desc->num_decoded_fmts)
+ return -EINVAL;
+
+ for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
+ if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
+ break;
+ }
+
+ if (i == coded_desc->num_decoded_fmts)
+ pix_mp->pixelformat = coded_desc->decoded_fmts[0];
+
+ /* always apply the frmsize constraint of the coded end */
+ v4l2_apply_frmsize_constraints(&pix_mp->width,
+ &pix_mp->height,
+ &coded_desc->frmsize);
+
+ tegra_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
+ pix_mp->width, pix_mp->height);
+ pix_mp->field = V4L2_FIELD_NONE;
+
+ return 0;
+}
+
+static int tegra_s_decoded_fmt(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
+ struct vb2_queue *vq;
+ int err;
+
+ /* change not allowed if queue is busy */
+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
+ V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
+ if (vb2_is_busy(vq))
+ return -EBUSY;
+
+ err = tegra_try_decoded_fmt(file, priv, f);
+ if (err)
+ return err;
+
+ ctx->decoded_fmt = *f;
+
+ return 0;
+}
+
+static int tegra_enum_coded_fmt(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
+ const struct tegra_vde_soc *soc = ctx->vde->soc;
+
+ if (f->index >= soc->num_coded_fmts)
+ return -EINVAL;
+
+ f->pixelformat = soc->coded_fmts[f->index].fourcc;
+
+ return 0;
+}
+
+static int tegra_g_coded_fmt(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
+
+ *f = ctx->coded_fmt;
+ return 0;
+}
+
+static const struct tegra_coded_fmt_desc *
+tegra_find_coded_fmt_desc(struct tegra_ctx *ctx, u32 fourcc)
+{
+ const struct tegra_vde_soc *soc = ctx->vde->soc;
+ unsigned int i;
+
+ for (i = 0; i < soc->num_coded_fmts; i++) {
+ if (soc->coded_fmts[i].fourcc == fourcc)
+ return &soc->coded_fmts[i];
+ }
+
+ return NULL;
+}
+
+static int tegra_try_coded_fmt(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
+ struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
+ const struct tegra_vde_soc *soc = ctx->vde->soc;
+ int size = pix_mp->plane_fmt[0].sizeimage;
+ const struct tegra_coded_fmt_desc *desc;
+
+ desc = tegra_find_coded_fmt_desc(ctx, pix_mp->pixelformat);
+ if (!desc) {
+ pix_mp->pixelformat = soc->coded_fmts[0].fourcc;
+ desc = &soc->coded_fmts[0];
+ }
+
+ v4l2_apply_frmsize_constraints(&pix_mp->width,
+ &pix_mp->height,
+ &desc->frmsize);
+
+ pix_mp->plane_fmt[0].sizeimage = max(ALIGN(size, SXE_BUFFER), SZ_2M);
+ pix_mp->field = V4L2_FIELD_NONE;
+ pix_mp->num_planes = 1;
+
+ return 0;
+}
+
+static int tegra_s_coded_fmt(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
+ const struct tegra_coded_fmt_desc *desc;
+ struct vb2_queue *peer_vq, *vq;
+ struct v4l2_format *cap_fmt;
+ int err;
+
+ /*
+ * In order to support dynamic resolution change, the decoder admits
+ * a resolution change, as long as the pixelformat remains. Can't be
+ * done if streaming.
+ */
+ vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
+ if (vb2_is_streaming(vq) ||
+ (vb2_is_busy(vq) &&
+ f->fmt.pix_mp.pixelformat != ctx->coded_fmt.fmt.pix_mp.pixelformat))
+ return -EBUSY;
+
+ /*
+ * Since format change on the OUTPUT queue will reset the CAPTURE
+ * queue, we can't allow doing so when the CAPTURE queue has buffers
+ * allocated.
+ */
+ peer_vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
+ if (vb2_is_busy(peer_vq))
+ return -EBUSY;
+
+ err = tegra_try_coded_fmt(file, priv, f);
+ if (err)
+ return err;
+
+ desc = tegra_find_coded_fmt_desc(ctx, f->fmt.pix_mp.pixelformat);
+ if (!desc)
+ return -EINVAL;
+
+ ctx->coded_fmt_desc = desc;
+ ctx->coded_fmt = *f;
+
+ /*
+ * Current decoded format might have become invalid with newly
+ * selected codec, so reset it to default just to be safe and
+ * keep internal driver state sane. User is mandated to set
+ * the decoded format again after we return, so we don't need
+ * anything smarter.
+ *
+ * Note that this will propagates any size changes to the decoded format.
+ */
+ tegra_reset_decoded_fmt(ctx);
+
+ /* propagate colorspace information to capture */
+ cap_fmt = &ctx->decoded_fmt;
+ cap_fmt->fmt.pix_mp.xfer_func = f->fmt.pix_mp.xfer_func;
+ cap_fmt->fmt.pix_mp.ycbcr_enc = f->fmt.pix_mp.ycbcr_enc;
+ cap_fmt->fmt.pix_mp.colorspace = f->fmt.pix_mp.colorspace;
+ cap_fmt->fmt.pix_mp.quantization = f->fmt.pix_mp.quantization;
+
+ return 0;
+}
+
+static int tegra_enum_framesizes(struct file *file, void *priv,
+ struct v4l2_frmsizeenum *fsize)
+{
+ struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
+ const struct tegra_coded_fmt_desc *fmt;
+
+ if (fsize->index)
+ return -EINVAL;
+
+ fmt = tegra_find_coded_fmt_desc(ctx, fsize->pixel_format);
+ if (!fmt)
+ return -EINVAL;
+
+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
+ fsize->stepwise = fmt->frmsize;
+
+ return 0;
+}
+
+static const struct v4l2_ioctl_ops tegra_v4l2_ioctl_ops = {
+ .vidioc_querycap = tegra_querycap,
+ .vidioc_enum_framesizes = tegra_enum_framesizes,
+
+ .vidioc_try_fmt_vid_out_mplane = tegra_try_coded_fmt,
+ .vidioc_g_fmt_vid_out_mplane = tegra_g_coded_fmt,
+ .vidioc_s_fmt_vid_out_mplane = tegra_s_coded_fmt,
+ .vidioc_enum_fmt_vid_out = tegra_enum_coded_fmt,
+
+ .vidioc_try_fmt_vid_cap_mplane = tegra_try_decoded_fmt,
+ .vidioc_g_fmt_vid_cap_mplane = tegra_g_decoded_fmt,
+ .vidioc_s_fmt_vid_cap_mplane = tegra_s_decoded_fmt,
+ .vidioc_enum_fmt_vid_cap = tegra_enum_decoded_fmt,
+
+ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
+ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
+ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
+ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
+ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
+ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
+ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
+
+ .vidioc_streamon = v4l2_m2m_ioctl_streamon,
+ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
+
+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+static int tegra_init_ctrls(struct tegra_ctx *ctx)
+{
+ unsigned int i;
+ int err;
+
+ err = v4l2_ctrl_handler_init(&ctx->hdl, ARRAY_SIZE(ctrl_cfgs));
+ if (err)
+ return err;
+
+ for (i = 0; i < ARRAY_SIZE(ctrl_cfgs); i++) {
+ ctx->ctrls[i] = v4l2_ctrl_new_custom(&ctx->hdl, &ctrl_cfgs[i],
+ NULL);
+ if (ctx->hdl.error) {
+ err = ctx->hdl.error;
+ goto free_ctrls;
+ }
+ }
+
+ err = v4l2_ctrl_handler_setup(&ctx->hdl);
+ if (err)
+ goto free_ctrls;
+
+ ctx->fh.ctrl_handler = &ctx->hdl;
+
+ return 0;
+
+free_ctrls:
+ v4l2_ctrl_handler_free(&ctx->hdl);
+
+ return err;
+}
+
+static int tegra_init_m2m(struct tegra_ctx *ctx)
+{
+ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(ctx->vde->m2m,
+ ctx, tegra_queue_init);
+ if (IS_ERR(ctx->fh.m2m_ctx))
+ return PTR_ERR(ctx->fh.m2m_ctx);
+
+ return 0;
+}
+
+static int tegra_open(struct file *file)
+{
+ struct tegra_vde *vde = video_drvdata(file);
+ struct tegra_ctx *ctx;
+ int err;
+
+ ctx = kzalloc(offsetof(struct tegra_ctx, ctrls[ARRAY_SIZE(ctrl_cfgs)]),
+ GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ ctx->vde = vde;
+ v4l2_fh_init(&ctx->fh, video_devdata(file));
+ INIT_WORK(&ctx->work, tegra_decode_complete);
+
+ err = tegra_init_ctrls(ctx);
+ if (err) {
+ v4l2_err(&vde->v4l2_dev, "failed to add controls: %d\n", err);
+ goto free_ctx;
+ }
+
+ err = tegra_init_m2m(ctx);
+ if (err) {
+ v4l2_err(&vde->v4l2_dev, "failed to initialize m2m: %d\n", err);
+ goto free_ctrls;
+ }
+
+ file->private_data = &ctx->fh;
+ v4l2_fh_add(&ctx->fh);
+
+ tegra_reset_coded_fmt(ctx);
+ tegra_try_coded_fmt(file, file->private_data, &ctx->coded_fmt);
+
+ tegra_reset_decoded_fmt(ctx);
+ tegra_try_decoded_fmt(file, file->private_data, &ctx->decoded_fmt);
+
+ return 0;
+
+free_ctrls:
+ v4l2_ctrl_handler_free(&ctx->hdl);
+free_ctx:
+ kfree(ctx);
+
+ return err;
+}
+
+static int tegra_release(struct file *file)
+{
+ struct v4l2_fh *fh = file->private_data;
+ struct tegra_ctx *ctx = fh_to_tegra_ctx(fh);
+ struct tegra_vde *vde = ctx->vde;
+
+ v4l2_fh_del(fh);
+ v4l2_m2m_ctx_release(fh->m2m_ctx);
+ v4l2_ctrl_handler_free(&ctx->hdl);
+ v4l2_fh_exit(fh);
+ kfree(ctx);
+
+ tegra_vde_dmabuf_cache_unmap_sync(vde);
+
+ return 0;
+}
+
+static const struct v4l2_file_operations tegra_v4l2_fops = {
+ .owner = THIS_MODULE,
+ .open = tegra_open,
+ .poll = v4l2_m2m_fop_poll,
+ .mmap = v4l2_m2m_fop_mmap,
+ .release = tegra_release,
+ .unlocked_ioctl = video_ioctl2,
+};
+
+static void tegra_device_run(void *priv)
+{
+ struct tegra_ctx *ctx = priv;
+ struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
+ struct media_request *src_req = src->vb2_buf.req_obj.req;
+ int err;
+
+ v4l2_ctrl_request_setup(src_req, &ctx->hdl);
+
+ err = ctx->coded_fmt_desc->decode_run(ctx);
+
+ v4l2_ctrl_request_complete(src_req, &ctx->hdl);
+
+ if (err)
+ tegra_job_finish(ctx, VB2_BUF_STATE_ERROR);
+ else
+ queue_work(ctx->vde->wq, &ctx->work);
+}
+
+static const struct v4l2_m2m_ops tegra_v4l2_m2m_ops = {
+ .device_run = tegra_device_run,
+};
+
+static int tegra_request_validate(struct media_request *req)
+{
+ unsigned int count;
+
+ count = vb2_request_buffer_cnt(req);
+ if (!count)
+ return -ENOENT;
+ else if (count > 1)
+ return -EINVAL;
+
+ return vb2_request_validate(req);
+}
+
+static const struct media_device_ops tegra_media_device_ops = {
+ .req_validate = tegra_request_validate,
+ .req_queue = v4l2_m2m_request_queue,
+};
+
+int tegra_vde_v4l2_init(struct tegra_vde *vde)
+{
+ struct device *dev = vde->dev;
+ int err;
+
+ mutex_init(&vde->v4l2_lock);
+ media_device_init(&vde->mdev);
+ video_set_drvdata(&vde->vdev, vde);
+
+ vde->vdev.lock = &vde->v4l2_lock,
+ vde->vdev.fops = &tegra_v4l2_fops,
+ vde->vdev.vfl_dir = VFL_DIR_M2M,
+ vde->vdev.release = video_device_release_empty,
+ vde->vdev.v4l2_dev = &vde->v4l2_dev;
+ vde->vdev.ioctl_ops = &tegra_v4l2_ioctl_ops,
+ vde->vdev.device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING,
+
+ vde->v4l2_dev.mdev = &vde->mdev;
+ vde->mdev.ops = &tegra_media_device_ops;
+ vde->mdev.dev = dev;
+
+ strscpy(vde->mdev.model, "tegra-vde", sizeof(vde->mdev.model));
+ strscpy(vde->vdev.name, "tegra-vde", sizeof(vde->vdev.name));
+ strscpy(vde->mdev.bus_info, "platform:tegra-vde",
+ sizeof(vde->mdev.bus_info));
+
+ vde->wq = create_workqueue("tegra-vde");
+ if (!vde->wq)
+ return -ENOMEM;
+
+ err = media_device_register(&vde->mdev);
+ if (err) {
+ dev_err(dev, "failed to register media device: %d\n", err);
+ goto clean_up_media_device;
+ }
+
+ err = v4l2_device_register(dev, &vde->v4l2_dev);
+ if (err) {
+ dev_err(dev, "failed to register v4l2 device: %d\n", err);
+ goto unreg_media_device;
+ }
+
+ err = video_register_device(&vde->vdev, VFL_TYPE_VIDEO, -1);
+ if (err) {
+ dev_err(dev, "failed to register video device: %d\n", err);
+ goto unreg_v4l2;
+ }
+
+ vde->m2m = v4l2_m2m_init(&tegra_v4l2_m2m_ops);
+ err = PTR_ERR_OR_ZERO(vde->m2m);
+ if (err) {
+ dev_err(dev, "failed to initialize m2m device: %d\n", err);
+ goto unreg_video_device;
+ }
+
+ err = v4l2_m2m_register_media_controller(vde->m2m, &vde->vdev,
+ MEDIA_ENT_F_PROC_VIDEO_DECODER);
+ if (err) {
+ dev_err(dev, "failed to register media controller: %d\n", err);
+ goto release_m2m;
+ }
+
+ v4l2_info(&vde->v4l2_dev, "v4l2 device registered as /dev/video%d\n",
+ vde->vdev.num);
+
+ return 0;
+
+release_m2m:
+ v4l2_m2m_release(vde->m2m);
+unreg_video_device:
+ video_unregister_device(&vde->vdev);
+unreg_v4l2:
+ v4l2_device_unregister(&vde->v4l2_dev);
+unreg_media_device:
+ media_device_unregister(&vde->mdev);
+clean_up_media_device:
+ media_device_cleanup(&vde->mdev);
+
+ destroy_workqueue(vde->wq);
+
+ return err;
+}
+
+void tegra_vde_v4l2_deinit(struct tegra_vde *vde)
+{
+ v4l2_m2m_unregister_media_controller(vde->m2m);
+ v4l2_m2m_release(vde->m2m);
+
+ video_unregister_device(&vde->vdev);
+ v4l2_device_unregister(&vde->v4l2_dev);
+
+ media_device_unregister(&vde->mdev);
+ media_device_cleanup(&vde->mdev);
+
+ destroy_workqueue(vde->wq);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NVIDIA Tegra Video decoder driver
+ *
+ * Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com>
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/dma-buf.h>
+#include <linux/genalloc.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+#include <soc/tegra/common.h>
+#include <soc/tegra/pmc.h>
+
+#include "vde.h"
+
+#define CREATE_TRACE_POINTS
+#include "trace.h"
+
+void tegra_vde_writel(struct tegra_vde *vde, u32 value,
+ void __iomem *base, u32 offset)
+{
+ trace_vde_writel(vde, base, offset, value);
+
+ writel_relaxed(value, base + offset);
+}
+
+u32 tegra_vde_readl(struct tegra_vde *vde, void __iomem *base, u32 offset)
+{
+ u32 value = readl_relaxed(base + offset);
+
+ trace_vde_readl(vde, base, offset, value);
+
+ return value;
+}
+
+void tegra_vde_set_bits(struct tegra_vde *vde, u32 mask,
+ void __iomem *base, u32 offset)
+{
+ u32 value = tegra_vde_readl(vde, base, offset);
+
+ tegra_vde_writel(vde, value | mask, base, offset);
+}
+
+int tegra_vde_alloc_bo(struct tegra_vde *vde,
+ struct tegra_vde_bo **ret_bo,
+ enum dma_data_direction dma_dir,
+ size_t size)
+{
+ struct device *dev = vde->dev;
+ struct tegra_vde_bo *bo;
+ int err;
+
+ bo = kzalloc(sizeof(*bo), GFP_KERNEL);
+ if (!bo)
+ return -ENOMEM;
+
+ bo->vde = vde;
+ bo->size = size;
+ bo->dma_dir = dma_dir;
+ bo->dma_attrs = DMA_ATTR_WRITE_COMBINE |
+ DMA_ATTR_NO_KERNEL_MAPPING;
+
+ if (!vde->domain)
+ bo->dma_attrs |= DMA_ATTR_FORCE_CONTIGUOUS;
+
+ bo->dma_cookie = dma_alloc_attrs(dev, bo->size, &bo->dma_handle,
+ GFP_KERNEL, bo->dma_attrs);
+ if (!bo->dma_cookie) {
+ dev_err(dev, "Failed to allocate DMA buffer of size: %zu\n",
+ bo->size);
+ err = -ENOMEM;
+ goto free_bo;
+ }
+
+ err = dma_get_sgtable_attrs(dev, &bo->sgt, bo->dma_cookie,
+ bo->dma_handle, bo->size, bo->dma_attrs);
+ if (err) {
+ dev_err(dev, "Failed to get DMA buffer SG table: %d\n", err);
+ goto free_attrs;
+ }
+
+ err = dma_map_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs);
+ if (err) {
+ dev_err(dev, "Failed to map DMA buffer SG table: %d\n", err);
+ goto free_table;
+ }
+
+ if (vde->domain) {
+ err = tegra_vde_iommu_map(vde, &bo->sgt, &bo->iova, bo->size);
+ if (err) {
+ dev_err(dev, "Failed to map DMA buffer IOVA: %d\n", err);
+ goto unmap_sgtable;
+ }
+
+ bo->dma_addr = iova_dma_addr(&vde->iova, bo->iova);
+ } else {
+ bo->dma_addr = sg_dma_address(bo->sgt.sgl);
+ }
+
+ *ret_bo = bo;
+
+ return 0;
+
+unmap_sgtable:
+ dma_unmap_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs);
+free_table:
+ sg_free_table(&bo->sgt);
+free_attrs:
+ dma_free_attrs(dev, bo->size, bo->dma_cookie, bo->dma_handle,
+ bo->dma_attrs);
+free_bo:
+ kfree(bo);
+
+ return err;
+}
+
+void tegra_vde_free_bo(struct tegra_vde_bo *bo)
+{
+ struct tegra_vde *vde = bo->vde;
+ struct device *dev = vde->dev;
+
+ if (vde->domain)
+ tegra_vde_iommu_unmap(vde, bo->iova);
+
+ dma_unmap_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs);
+
+ sg_free_table(&bo->sgt);
+
+ dma_free_attrs(dev, bo->size, bo->dma_cookie, bo->dma_handle,
+ bo->dma_attrs);
+ kfree(bo);
+}
+
+static irqreturn_t tegra_vde_isr(int irq, void *data)
+{
+ struct tegra_vde *vde = data;
+
+ if (completion_done(&vde->decode_completion))
+ return IRQ_NONE;
+
+ tegra_vde_set_bits(vde, 0, vde->frameid, 0x208);
+ complete(&vde->decode_completion);
+
+ return IRQ_HANDLED;
+}
+
+static __maybe_unused int tegra_vde_runtime_suspend(struct device *dev)
+{
+ struct tegra_vde *vde = dev_get_drvdata(dev);
+ int err;
+
+ if (!dev->pm_domain) {
+ err = tegra_powergate_power_off(TEGRA_POWERGATE_VDEC);
+ if (err) {
+ dev_err(dev, "Failed to power down HW: %d\n", err);
+ return err;
+ }
+ }
+
+ clk_disable_unprepare(vde->clk);
+ reset_control_release(vde->rst);
+ reset_control_release(vde->rst_mc);
+
+ return 0;
+}
+
+static __maybe_unused int tegra_vde_runtime_resume(struct device *dev)
+{
+ struct tegra_vde *vde = dev_get_drvdata(dev);
+ int err;
+
+ err = reset_control_acquire(vde->rst_mc);
+ if (err) {
+ dev_err(dev, "Failed to acquire mc reset: %d\n", err);
+ return err;
+ }
+
+ err = reset_control_acquire(vde->rst);
+ if (err) {
+ dev_err(dev, "Failed to acquire reset: %d\n", err);
+ goto release_mc_reset;
+ }
+
+ if (!dev->pm_domain) {
+ err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_VDEC,
+ vde->clk, vde->rst);
+ if (err) {
+ dev_err(dev, "Failed to power up HW : %d\n", err);
+ goto release_reset;
+ }
+ } else {
+ /*
+ * tegra_powergate_sequence_power_up() leaves clocks enabled,
+ * while GENPD not.
+ */
+ err = clk_prepare_enable(vde->clk);
+ if (err) {
+ dev_err(dev, "Failed to enable clock: %d\n", err);
+ goto release_reset;
+ }
+ }
+
+ return 0;
+
+release_reset:
+ reset_control_release(vde->rst);
+release_mc_reset:
+ reset_control_release(vde->rst_mc);
+
+ return err;
+}
+
+static int tegra_vde_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct tegra_vde *vde;
+ int irq, err;
+
+ vde = devm_kzalloc(dev, sizeof(*vde), GFP_KERNEL);
+ if (!vde)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, vde);
+
+ vde->soc = of_device_get_match_data(&pdev->dev);
+ vde->dev = dev;
+
+ vde->sxe = devm_platform_ioremap_resource_byname(pdev, "sxe");
+ if (IS_ERR(vde->sxe))
+ return PTR_ERR(vde->sxe);
+
+ vde->bsev = devm_platform_ioremap_resource_byname(pdev, "bsev");
+ if (IS_ERR(vde->bsev))
+ return PTR_ERR(vde->bsev);
+
+ vde->mbe = devm_platform_ioremap_resource_byname(pdev, "mbe");
+ if (IS_ERR(vde->mbe))
+ return PTR_ERR(vde->mbe);
+
+ vde->ppe = devm_platform_ioremap_resource_byname(pdev, "ppe");
+ if (IS_ERR(vde->ppe))
+ return PTR_ERR(vde->ppe);
+
+ vde->mce = devm_platform_ioremap_resource_byname(pdev, "mce");
+ if (IS_ERR(vde->mce))
+ return PTR_ERR(vde->mce);
+
+ vde->tfe = devm_platform_ioremap_resource_byname(pdev, "tfe");
+ if (IS_ERR(vde->tfe))
+ return PTR_ERR(vde->tfe);
+
+ vde->ppb = devm_platform_ioremap_resource_byname(pdev, "ppb");
+ if (IS_ERR(vde->ppb))
+ return PTR_ERR(vde->ppb);
+
+ vde->vdma = devm_platform_ioremap_resource_byname(pdev, "vdma");
+ if (IS_ERR(vde->vdma))
+ return PTR_ERR(vde->vdma);
+
+ vde->frameid = devm_platform_ioremap_resource_byname(pdev, "frameid");
+ if (IS_ERR(vde->frameid))
+ return PTR_ERR(vde->frameid);
+
+ vde->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(vde->clk)) {
+ err = PTR_ERR(vde->clk);
+ dev_err(dev, "Could not get VDE clk %d\n", err);
+ return err;
+ }
+
+ vde->rst = devm_reset_control_get_exclusive_released(dev, NULL);
+ if (IS_ERR(vde->rst)) {
+ err = PTR_ERR(vde->rst);
+ dev_err(dev, "Could not get VDE reset %d\n", err);
+ return err;
+ }
+
+ vde->rst_mc = devm_reset_control_get_optional_exclusive_released(dev, "mc");
+ if (IS_ERR(vde->rst_mc)) {
+ err = PTR_ERR(vde->rst_mc);
+ dev_err(dev, "Could not get MC reset %d\n", err);
+ return err;
+ }
+
+ irq = platform_get_irq_byname(pdev, "sync-token");
+ if (irq < 0)
+ return irq;
+
+ err = devm_request_irq(dev, irq, tegra_vde_isr, 0,
+ dev_name(dev), vde);
+ if (err) {
+ dev_err(dev, "Could not request IRQ %d\n", err);
+ return err;
+ }
+
+ err = devm_tegra_core_dev_init_opp_table_common(dev);
+ if (err) {
+ dev_err(dev, "Could initialize OPP table %d\n", err);
+ return err;
+ }
+
+ vde->iram_pool = of_gen_pool_get(dev->of_node, "iram", 0);
+ if (!vde->iram_pool) {
+ dev_err(dev, "Could not get IRAM pool\n");
+ return -EPROBE_DEFER;
+ }
+
+ vde->iram = gen_pool_dma_alloc(vde->iram_pool,
+ gen_pool_size(vde->iram_pool),
+ &vde->iram_lists_addr);
+ if (!vde->iram) {
+ dev_err(dev, "Could not reserve IRAM\n");
+ return -ENOMEM;
+ }
+
+ INIT_LIST_HEAD(&vde->map_list);
+ mutex_init(&vde->map_lock);
+ mutex_init(&vde->lock);
+ init_completion(&vde->decode_completion);
+
+ err = tegra_vde_iommu_init(vde);
+ if (err) {
+ dev_err(dev, "Failed to initialize IOMMU: %d\n", err);
+ goto err_gen_free;
+ }
+
+ pm_runtime_enable(dev);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_set_autosuspend_delay(dev, 300);
+
+ /*
+ * VDE partition may be left ON after bootloader, hence let's
+ * power-cycle it in order to put hardware into a predictable lower
+ * power state.
+ */
+ err = pm_runtime_resume_and_get(dev);
+ if (err)
+ goto err_pm_runtime;
+
+ pm_runtime_put(dev);
+
+ err = tegra_vde_alloc_bo(vde, &vde->secure_bo, DMA_FROM_DEVICE, 4096);
+ if (err) {
+ dev_err(dev, "Failed to allocate secure BO: %d\n", err);
+ goto err_pm_runtime;
+ }
+
+ err = tegra_vde_v4l2_init(vde);
+ if (err) {
+ dev_err(dev, "Failed to initialize V4L2: %d\n", err);
+ goto err_free_secure_bo;
+ }
+
+ return 0;
+
+err_free_secure_bo:
+ tegra_vde_free_bo(vde->secure_bo);
+err_pm_runtime:
+ pm_runtime_dont_use_autosuspend(dev);
+ pm_runtime_disable(dev);
+
+ tegra_vde_iommu_deinit(vde);
+
+err_gen_free:
+ gen_pool_free(vde->iram_pool, (unsigned long)vde->iram,
+ gen_pool_size(vde->iram_pool));
+
+ return err;
+}
+
+static int tegra_vde_remove(struct platform_device *pdev)
+{
+ struct tegra_vde *vde = platform_get_drvdata(pdev);
+ struct device *dev = &pdev->dev;
+
+ tegra_vde_v4l2_deinit(vde);
+ tegra_vde_free_bo(vde->secure_bo);
+
+ /*
+ * As it increments RPM usage_count even on errors, we don't need to
+ * check the returned code here.
+ */
+ pm_runtime_get_sync(dev);
+
+ pm_runtime_dont_use_autosuspend(dev);
+ pm_runtime_disable(dev);
+
+ /*
+ * Balance RPM state, the VDE power domain is left ON and hardware
+ * is clock-gated. It's safe to reboot machine now.
+ */
+ pm_runtime_put_noidle(dev);
+ clk_disable_unprepare(vde->clk);
+
+ tegra_vde_dmabuf_cache_unmap_all(vde);
+ tegra_vde_iommu_deinit(vde);
+
+ gen_pool_free(vde->iram_pool, (unsigned long)vde->iram,
+ gen_pool_size(vde->iram_pool));
+
+ return 0;
+}
+
+static void tegra_vde_shutdown(struct platform_device *pdev)
+{
+ /*
+ * On some devices bootloader isn't ready to a power-gated VDE on
+ * a warm-reboot, machine will hang in that case.
+ */
+ pm_runtime_get_sync(&pdev->dev);
+}
+
+static __maybe_unused int tegra_vde_pm_suspend(struct device *dev)
+{
+ struct tegra_vde *vde = dev_get_drvdata(dev);
+ int err;
+
+ mutex_lock(&vde->lock);
+
+ err = pm_runtime_force_suspend(dev);
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
+static __maybe_unused int tegra_vde_pm_resume(struct device *dev)
+{
+ struct tegra_vde *vde = dev_get_drvdata(dev);
+ int err;
+
+ err = pm_runtime_force_resume(dev);
+ if (err < 0)
+ return err;
+
+ mutex_unlock(&vde->lock);
+
+ return 0;
+}
+
+static const struct dev_pm_ops tegra_vde_pm_ops = {
+ SET_RUNTIME_PM_OPS(tegra_vde_runtime_suspend,
+ tegra_vde_runtime_resume,
+ NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(tegra_vde_pm_suspend,
+ tegra_vde_pm_resume)
+};
+
+static const u32 tegra124_decoded_fmts[] = {
+ /* TBD: T124 supports only a non-standard Tegra tiled format */
+};
+
+static const struct tegra_coded_fmt_desc tegra124_coded_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_H264_SLICE,
+ .frmsize = {
+ .min_width = 16,
+ .max_width = 1920,
+ .step_width = 16,
+ .min_height = 16,
+ .max_height = 2032,
+ .step_height = 16,
+ },
+ .num_decoded_fmts = ARRAY_SIZE(tegra124_decoded_fmts),
+ .decoded_fmts = tegra124_decoded_fmts,
+ .decode_run = tegra_vde_h264_decode_run,
+ .decode_wait = tegra_vde_h264_decode_wait,
+ },
+};
+
+static const u32 tegra20_decoded_fmts[] = {
+ V4L2_PIX_FMT_YUV420M,
+ V4L2_PIX_FMT_YVU420M,
+};
+
+static const struct tegra_coded_fmt_desc tegra20_coded_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_H264_SLICE,
+ .frmsize = {
+ .min_width = 16,
+ .max_width = 1920,
+ .step_width = 16,
+ .min_height = 16,
+ .max_height = 2032,
+ .step_height = 16,
+ },
+ .num_decoded_fmts = ARRAY_SIZE(tegra20_decoded_fmts),
+ .decoded_fmts = tegra20_decoded_fmts,
+ .decode_run = tegra_vde_h264_decode_run,
+ .decode_wait = tegra_vde_h264_decode_wait,
+ },
+};
+
+static const struct tegra_vde_soc tegra124_vde_soc = {
+ .supports_ref_pic_marking = true,
+ .coded_fmts = tegra124_coded_fmts,
+ .num_coded_fmts = ARRAY_SIZE(tegra124_coded_fmts),
+};
+
+static const struct tegra_vde_soc tegra114_vde_soc = {
+ .supports_ref_pic_marking = true,
+ .coded_fmts = tegra20_coded_fmts,
+ .num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts),
+};
+
+static const struct tegra_vde_soc tegra30_vde_soc = {
+ .supports_ref_pic_marking = false,
+ .coded_fmts = tegra20_coded_fmts,
+ .num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts),
+};
+
+static const struct tegra_vde_soc tegra20_vde_soc = {
+ .supports_ref_pic_marking = false,
+ .coded_fmts = tegra20_coded_fmts,
+ .num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts),
+};
+
+static const struct of_device_id tegra_vde_of_match[] = {
+ { .compatible = "nvidia,tegra124-vde", .data = &tegra124_vde_soc },
+ { .compatible = "nvidia,tegra114-vde", .data = &tegra114_vde_soc },
+ { .compatible = "nvidia,tegra30-vde", .data = &tegra30_vde_soc },
+ { .compatible = "nvidia,tegra20-vde", .data = &tegra20_vde_soc },
+ { },
+};
+MODULE_DEVICE_TABLE(of, tegra_vde_of_match);
+
+static struct platform_driver tegra_vde_driver = {
+ .probe = tegra_vde_probe,
+ .remove = tegra_vde_remove,
+ .shutdown = tegra_vde_shutdown,
+ .driver = {
+ .name = "tegra-vde",
+ .of_match_table = tegra_vde_of_match,
+ .pm = &tegra_vde_pm_ops,
+ },
+};
+module_platform_driver(tegra_vde_driver);
+
+MODULE_DESCRIPTION("NVIDIA Tegra Video Decoder driver");
+MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
+MODULE_LICENSE("GPL");
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * NVIDIA Tegra Video decoder driver
+ *
+ * Copyright (C) 2016-2019 GRATE-DRIVER project
+ */
+
+#ifndef TEGRA_VDE_H
+#define TEGRA_VDE_H
+
+#include <linux/completion.h>
+#include <linux/dma-direction.h>
+#include <linux/iova.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#include <media/media-device.h>
+#include <media/videobuf2-dma-contig.h>
+#include <media/videobuf2-dma-sg.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mem2mem.h>
+
+#define ICMDQUE_WR 0x00
+#define CMDQUE_CONTROL 0x08
+#define INTR_STATUS 0x18
+#define BSE_INT_ENB 0x40
+#define BSE_CONFIG 0x44
+
+#define BSE_ICMDQUE_EMPTY BIT(3)
+#define BSE_DMA_BUSY BIT(23)
+
+#define BSEV_ALIGN SZ_1
+#define FRAMEID_ALIGN SZ_256
+#define SXE_BUFFER SZ_32K
+#define VDE_ATOM SZ_16
+
+struct clk;
+struct dma_buf;
+struct gen_pool;
+struct tegra_ctx;
+struct iommu_group;
+struct iommu_domain;
+struct reset_control;
+struct dma_buf_attachment;
+struct tegra_vde_h264_frame;
+struct tegra_vde_h264_decoder_ctx;
+
+struct tegra_video_frame {
+ struct dma_buf_attachment *y_dmabuf_attachment;
+ struct dma_buf_attachment *cb_dmabuf_attachment;
+ struct dma_buf_attachment *cr_dmabuf_attachment;
+ struct dma_buf_attachment *aux_dmabuf_attachment;
+ dma_addr_t y_addr;
+ dma_addr_t cb_addr;
+ dma_addr_t cr_addr;
+ dma_addr_t aux_addr;
+ u32 frame_num;
+ u32 flags;
+ u32 luma_atoms_pitch;
+ u32 chroma_atoms_pitch;
+};
+
+struct tegra_coded_fmt_desc {
+ u32 fourcc;
+ struct v4l2_frmsize_stepwise frmsize;
+ unsigned int num_decoded_fmts;
+ const u32 *decoded_fmts;
+ int (*decode_run)(struct tegra_ctx *ctx);
+ int (*decode_wait)(struct tegra_ctx *ctx);
+};
+
+struct tegra_vde_soc {
+ bool supports_ref_pic_marking;
+ const struct tegra_coded_fmt_desc *coded_fmts;
+ u32 num_coded_fmts;
+};
+
+struct tegra_vde_bo {
+ struct iova *iova;
+ struct sg_table sgt;
+ struct tegra_vde *vde;
+ enum dma_data_direction dma_dir;
+ unsigned long dma_attrs;
+ dma_addr_t dma_handle;
+ dma_addr_t dma_addr;
+ void *dma_cookie;
+ size_t size;
+};
+
+struct tegra_vde {
+ void __iomem *sxe;
+ void __iomem *bsev;
+ void __iomem *mbe;
+ void __iomem *ppe;
+ void __iomem *mce;
+ void __iomem *tfe;
+ void __iomem *ppb;
+ void __iomem *vdma;
+ void __iomem *frameid;
+ struct device *dev;
+ struct mutex lock;
+ struct mutex map_lock;
+ struct list_head map_list;
+ struct reset_control *rst;
+ struct reset_control *rst_mc;
+ struct gen_pool *iram_pool;
+ struct completion decode_completion;
+ struct clk *clk;
+ struct iommu_domain *domain;
+ struct iommu_group *group;
+ struct iova_domain iova;
+ struct iova *iova_resv_static_addresses;
+ struct iova *iova_resv_last_page;
+ const struct tegra_vde_soc *soc;
+ struct tegra_vde_bo *secure_bo;
+ dma_addr_t bitstream_data_addr;
+ dma_addr_t iram_lists_addr;
+ u32 *iram;
+ struct v4l2_device v4l2_dev;
+ struct v4l2_m2m_dev *m2m;
+ struct media_device mdev;
+ struct video_device vdev;
+ struct mutex v4l2_lock;
+ struct workqueue_struct *wq;
+ struct tegra_video_frame frames[V4L2_H264_NUM_DPB_ENTRIES + 1];
+};
+
+int tegra_vde_alloc_bo(struct tegra_vde *vde,
+ struct tegra_vde_bo **ret_bo,
+ enum dma_data_direction dma_dir,
+ size_t size);
+void tegra_vde_free_bo(struct tegra_vde_bo *bo);
+
+struct tegra_ctx_h264 {
+ const struct v4l2_ctrl_h264_decode_params *decode_params;
+ const struct v4l2_ctrl_h264_sps *sps;
+ const struct v4l2_ctrl_h264_pps *pps;
+};
+
+struct tegra_ctx {
+ struct tegra_vde *vde;
+ struct tegra_ctx_h264 h264;
+ struct work_struct work;
+ struct v4l2_fh fh;
+ struct v4l2_ctrl_handler hdl;
+ struct v4l2_format coded_fmt;
+ struct v4l2_format decoded_fmt;
+ const struct tegra_coded_fmt_desc *coded_fmt_desc;
+ struct v4l2_ctrl *ctrls[];
+};
+
+struct tegra_m2m_buffer {
+ struct v4l2_m2m_buffer m2m;
+ struct dma_buf_attachment *a[VB2_MAX_PLANES];
+ dma_addr_t dma_base[VB2_MAX_PLANES];
+ dma_addr_t dma_addr[VB2_MAX_PLANES];
+ struct iova *iova[VB2_MAX_PLANES];
+ struct tegra_vde_bo *aux;
+ bool b_frame;
+};
+
+static inline struct tegra_m2m_buffer *
+vb_to_tegra_buf(struct vb2_buffer *vb)
+{
+ struct v4l2_m2m_buffer *m2m = container_of(vb, struct v4l2_m2m_buffer,
+ vb.vb2_buf);
+
+ return container_of(m2m, struct tegra_m2m_buffer, m2m);
+}
+
+void tegra_vde_prepare_control_data(struct tegra_ctx *ctx, u32 id);
+
+void tegra_vde_writel(struct tegra_vde *vde, u32 value, void __iomem *base,
+ u32 offset);
+u32 tegra_vde_readl(struct tegra_vde *vde, void __iomem *base, u32 offset);
+void tegra_vde_set_bits(struct tegra_vde *vde, u32 mask, void __iomem *base,
+ u32 offset);
+
+int tegra_vde_h264_decode_run(struct tegra_ctx *ctx);
+int tegra_vde_h264_decode_wait(struct tegra_ctx *ctx);
+
+int tegra_vde_iommu_init(struct tegra_vde *vde);
+void tegra_vde_iommu_deinit(struct tegra_vde *vde);
+int tegra_vde_iommu_map(struct tegra_vde *vde,
+ struct sg_table *sgt,
+ struct iova **iovap,
+ size_t size);
+void tegra_vde_iommu_unmap(struct tegra_vde *vde, struct iova *iova);
+
+int tegra_vde_dmabuf_cache_map(struct tegra_vde *vde,
+ struct dma_buf *dmabuf,
+ enum dma_data_direction dma_dir,
+ struct dma_buf_attachment **ap,
+ dma_addr_t *addrp);
+void tegra_vde_dmabuf_cache_unmap(struct tegra_vde *vde,
+ struct dma_buf_attachment *a,
+ bool release);
+void tegra_vde_dmabuf_cache_unmap_sync(struct tegra_vde *vde);
+void tegra_vde_dmabuf_cache_unmap_all(struct tegra_vde *vde);
+
+static __maybe_unused char const *
+tegra_vde_reg_base_name(struct tegra_vde *vde, void __iomem *base)
+{
+ if (vde->sxe == base)
+ return "SXE";
+
+ if (vde->bsev == base)
+ return "BSEV";
+
+ if (vde->mbe == base)
+ return "MBE";
+
+ if (vde->ppe == base)
+ return "PPE";
+
+ if (vde->mce == base)
+ return "MCE";
+
+ if (vde->tfe == base)
+ return "TFE";
+
+ if (vde->ppb == base)
+ return "PPB";
+
+ if (vde->vdma == base)
+ return "VDMA";
+
+ if (vde->frameid == base)
+ return "FRAMEID";
+
+ return "???";
+}
+
+int tegra_vde_v4l2_init(struct tegra_vde *vde);
+void tegra_vde_v4l2_deinit(struct tegra_vde *vde);
+
+#endif /* TEGRA_VDE_H */
+++ /dev/null
-config VIDEO_TEGRA_VDE
- tristate "NVIDIA Tegra Video Decoder Engine driver"
- depends on V4L_MEM2MEM_DRIVERS
- depends on ARCH_TEGRA || COMPILE_TEST
- depends on VIDEO_DEV && VIDEO_V4L2
- select DMA_SHARED_BUFFER
- select IOMMU_IOVA
- select MEDIA_CONTROLLER
- select MEDIA_CONTROLLER_REQUEST_API
- select SRAM
- select VIDEOBUF2_DMA_CONTIG
- select VIDEOBUF2_DMA_SG
- select V4L2_H264
- select V4L2_MEM2MEM_DEV
- help
- Support for the NVIDIA Tegra video decoder unit.
- To compile this driver as a module choose m here.
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-tegra-vde-y := vde.o iommu.o dmabuf-cache.o h264.o v4l2.o
-obj-$(CONFIG_VIDEO_TEGRA_VDE) += tegra-vde.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * NVIDIA Tegra Video decoder driver
- *
- * Copyright (C) 2016-2019 GRATE-DRIVER project
- */
-
-#include <linux/dma-buf.h>
-#include <linux/iova.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/workqueue.h>
-#include <linux/module.h>
-
-#include "vde.h"
-
-MODULE_IMPORT_NS(DMA_BUF);
-
-struct tegra_vde_cache_entry {
- enum dma_data_direction dma_dir;
- struct dma_buf_attachment *a;
- struct delayed_work dwork;
- struct tegra_vde *vde;
- struct list_head list;
- struct sg_table *sgt;
- struct iova *iova;
- unsigned int refcnt;
-};
-
-static void tegra_vde_release_entry(struct tegra_vde_cache_entry *entry)
-{
- struct dma_buf *dmabuf = entry->a->dmabuf;
-
- WARN_ON_ONCE(entry->refcnt);
-
- if (entry->vde->domain)
- tegra_vde_iommu_unmap(entry->vde, entry->iova);
-
- dma_buf_unmap_attachment(entry->a, entry->sgt, entry->dma_dir);
- dma_buf_detach(dmabuf, entry->a);
- dma_buf_put(dmabuf);
-
- list_del(&entry->list);
- kfree(entry);
-}
-
-static void tegra_vde_delayed_unmap(struct work_struct *work)
-{
- struct tegra_vde_cache_entry *entry;
- struct tegra_vde *vde;
-
- entry = container_of(work, struct tegra_vde_cache_entry,
- dwork.work);
- vde = entry->vde;
-
- mutex_lock(&vde->map_lock);
- tegra_vde_release_entry(entry);
- mutex_unlock(&vde->map_lock);
-}
-
-int tegra_vde_dmabuf_cache_map(struct tegra_vde *vde,
- struct dma_buf *dmabuf,
- enum dma_data_direction dma_dir,
- struct dma_buf_attachment **ap,
- dma_addr_t *addrp)
-{
- struct dma_buf_attachment *attachment;
- struct tegra_vde_cache_entry *entry;
- struct device *dev = vde->dev;
- struct sg_table *sgt;
- struct iova *iova;
- int err;
-
- mutex_lock(&vde->map_lock);
-
- list_for_each_entry(entry, &vde->map_list, list) {
- if (entry->a->dmabuf != dmabuf)
- continue;
-
- if (!cancel_delayed_work(&entry->dwork))
- continue;
-
- if (entry->dma_dir != dma_dir)
- entry->dma_dir = DMA_BIDIRECTIONAL;
-
- dma_buf_put(dmabuf);
-
- if (vde->domain)
- *addrp = iova_dma_addr(&vde->iova, entry->iova);
- else
- *addrp = sg_dma_address(entry->sgt->sgl);
-
- goto ref;
- }
-
- attachment = dma_buf_attach(dmabuf, dev);
- if (IS_ERR(attachment)) {
- dev_err(dev, "Failed to attach dmabuf\n");
- err = PTR_ERR(attachment);
- goto err_unlock;
- }
-
- sgt = dma_buf_map_attachment(attachment, dma_dir);
- if (IS_ERR(sgt)) {
- dev_err(dev, "Failed to get dmabufs sg_table\n");
- err = PTR_ERR(sgt);
- goto err_detach;
- }
-
- if (!vde->domain && sgt->nents > 1) {
- dev_err(dev, "Sparse DMA region is unsupported, please enable IOMMU\n");
- err = -EINVAL;
- goto err_unmap;
- }
-
- entry = kzalloc(sizeof(*entry), GFP_KERNEL);
- if (!entry) {
- err = -ENOMEM;
- goto err_unmap;
- }
-
- if (vde->domain) {
- err = tegra_vde_iommu_map(vde, sgt, &iova, dmabuf->size);
- if (err)
- goto err_free;
-
- *addrp = iova_dma_addr(&vde->iova, iova);
- } else {
- *addrp = sg_dma_address(sgt->sgl);
- iova = NULL;
- }
-
- INIT_DELAYED_WORK(&entry->dwork, tegra_vde_delayed_unmap);
- list_add(&entry->list, &vde->map_list);
-
- entry->dma_dir = dma_dir;
- entry->iova = iova;
- entry->vde = vde;
- entry->sgt = sgt;
- entry->a = attachment;
-ref:
- entry->refcnt++;
-
- *ap = entry->a;
-
- mutex_unlock(&vde->map_lock);
-
- return 0;
-
-err_free:
- kfree(entry);
-err_unmap:
- dma_buf_unmap_attachment(attachment, sgt, dma_dir);
-err_detach:
- dma_buf_detach(dmabuf, attachment);
-err_unlock:
- mutex_unlock(&vde->map_lock);
-
- return err;
-}
-
-void tegra_vde_dmabuf_cache_unmap(struct tegra_vde *vde,
- struct dma_buf_attachment *a,
- bool release)
-{
- struct tegra_vde_cache_entry *entry;
-
- mutex_lock(&vde->map_lock);
-
- list_for_each_entry(entry, &vde->map_list, list) {
- if (entry->a != a)
- continue;
-
- WARN_ON_ONCE(!entry->refcnt);
-
- if (--entry->refcnt == 0) {
- if (release)
- tegra_vde_release_entry(entry);
- else
- schedule_delayed_work(&entry->dwork, 5 * HZ);
- }
- break;
- }
-
- mutex_unlock(&vde->map_lock);
-}
-
-void tegra_vde_dmabuf_cache_unmap_sync(struct tegra_vde *vde)
-{
- struct tegra_vde_cache_entry *entry, *tmp;
-
- mutex_lock(&vde->map_lock);
-
- list_for_each_entry_safe(entry, tmp, &vde->map_list, list) {
- if (entry->refcnt)
- continue;
-
- if (!cancel_delayed_work(&entry->dwork))
- continue;
-
- tegra_vde_release_entry(entry);
- }
-
- mutex_unlock(&vde->map_lock);
-}
-
-void tegra_vde_dmabuf_cache_unmap_all(struct tegra_vde *vde)
-{
- struct tegra_vde_cache_entry *entry, *tmp;
-
- mutex_lock(&vde->map_lock);
-
- while (!list_empty(&vde->map_list)) {
- list_for_each_entry_safe(entry, tmp, &vde->map_list, list) {
- if (!cancel_delayed_work(&entry->dwork))
- continue;
-
- tegra_vde_release_entry(entry);
- }
-
- mutex_unlock(&vde->map_lock);
- schedule();
- mutex_lock(&vde->map_lock);
- }
-
- mutex_unlock(&vde->map_lock);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * NVIDIA Tegra Video decoder driver
- *
- * Copyright (C) 2016-2022 Dmitry Osipenko <digetx@gmail.com>
- *
- */
-
-#include <linux/iopoll.h>
-#include <linux/pm_runtime.h>
-#include <linux/reset.h>
-#include <linux/slab.h>
-
-#include <media/v4l2-h264.h>
-
-#include "trace.h"
-#include "vde.h"
-
-#define FLAG_B_FRAME 0x1
-#define FLAG_REFERENCE 0x2
-
-struct tegra_vde_h264_frame {
- unsigned int frame_num;
- unsigned int flags;
-};
-
-struct tegra_vde_h264_decoder_ctx {
- unsigned int dpb_frames_nb;
- unsigned int dpb_ref_frames_with_earlier_poc_nb;
- unsigned int baseline_profile;
- unsigned int level_idc;
- unsigned int log2_max_pic_order_cnt_lsb;
- unsigned int log2_max_frame_num;
- unsigned int pic_order_cnt_type;
- unsigned int direct_8x8_inference_flag;
- unsigned int pic_width_in_mbs;
- unsigned int pic_height_in_mbs;
- unsigned int pic_init_qp;
- unsigned int deblocking_filter_control_present_flag;
- unsigned int constrained_intra_pred_flag;
- unsigned int chroma_qp_index_offset;
- unsigned int pic_order_present_flag;
- unsigned int num_ref_idx_l0_active_minus1;
- unsigned int num_ref_idx_l1_active_minus1;
-};
-
-struct h264_reflists {
- u8 p[V4L2_H264_NUM_DPB_ENTRIES];
- u8 b0[V4L2_H264_NUM_DPB_ENTRIES];
- u8 b1[V4L2_H264_NUM_DPB_ENTRIES];
-};
-
-static int tegra_vde_wait_mbe(struct tegra_vde *vde)
-{
- u32 tmp;
-
- return readl_relaxed_poll_timeout(vde->mbe + 0x8C, tmp,
- tmp >= 0x10, 1, 100);
-}
-
-static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde,
- unsigned int refs_nb,
- bool setup_refs)
-{
- u32 value, frame_idx_enb_mask = 0;
- unsigned int frame_idx;
- unsigned int idx;
- int err;
-
- tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80);
- tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80);
-
- err = tegra_vde_wait_mbe(vde);
- if (err)
- return err;
-
- if (!setup_refs)
- return 0;
-
- for (idx = 0, frame_idx = 1; idx < refs_nb; idx++, frame_idx++) {
- tegra_vde_writel(vde, 0xD0000000 | (frame_idx << 23),
- vde->mbe, 0x80);
- tegra_vde_writel(vde, 0xD0200000 | (frame_idx << 23),
- vde->mbe, 0x80);
-
- frame_idx_enb_mask |= frame_idx << (6 * (idx % 4));
-
- if (idx % 4 == 3 || idx == refs_nb - 1) {
- value = 0xC0000000;
- value |= (idx >> 2) << 24;
- value |= frame_idx_enb_mask;
-
- tegra_vde_writel(vde, value, vde->mbe, 0x80);
-
- err = tegra_vde_wait_mbe(vde);
- if (err)
- return err;
-
- frame_idx_enb_mask = 0;
- }
- }
-
- return 0;
-}
-
-static void tegra_vde_mbe_set_0xa_reg(struct tegra_vde *vde, int reg, u32 val)
-{
- tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF),
- vde->mbe, 0x80);
- tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16),
- vde->mbe, 0x80);
-}
-
-static int tegra_vde_wait_bsev(struct tegra_vde *vde, bool wait_dma)
-{
- struct device *dev = vde->dev;
- u32 value;
- int err;
-
- err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
- !(value & BIT(2)), 1, 100);
- if (err) {
- dev_err(dev, "BSEV unknown bit timeout\n");
- return err;
- }
-
- err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
- (value & BSE_ICMDQUE_EMPTY), 1, 100);
- if (err) {
- dev_err(dev, "BSEV ICMDQUE flush timeout\n");
- return err;
- }
-
- if (!wait_dma)
- return 0;
-
- err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
- !(value & BSE_DMA_BUSY), 1, 1000);
- if (err) {
- dev_err(dev, "BSEV DMA timeout\n");
- return err;
- }
-
- return 0;
-}
-
-static int tegra_vde_push_to_bsev_icmdqueue(struct tegra_vde *vde,
- u32 value, bool wait_dma)
-{
- tegra_vde_writel(vde, value, vde->bsev, ICMDQUE_WR);
-
- return tegra_vde_wait_bsev(vde, wait_dma);
-}
-
-static void tegra_vde_setup_frameid(struct tegra_vde *vde,
- struct tegra_video_frame *frame,
- unsigned int frameid,
- u32 mbs_width, u32 mbs_height)
-{
- u32 y_addr = frame ? frame->y_addr : 0x6CDEAD00;
- u32 cb_addr = frame ? frame->cb_addr : 0x6CDEAD00;
- u32 cr_addr = frame ? frame->cr_addr : 0x6CDEAD00;
- u32 value1 = frame ? ((frame->luma_atoms_pitch << 16) | mbs_height) : 0;
- u32 value2 = frame ? ((frame->chroma_atoms_pitch << 6) | 1) : 0;
-
- tegra_vde_writel(vde, y_addr >> 8, vde->frameid, 0x000 + frameid * 4);
- tegra_vde_writel(vde, cb_addr >> 8, vde->frameid, 0x100 + frameid * 4);
- tegra_vde_writel(vde, cr_addr >> 8, vde->frameid, 0x180 + frameid * 4);
- tegra_vde_writel(vde, value1, vde->frameid, 0x080 + frameid * 4);
- tegra_vde_writel(vde, value2, vde->frameid, 0x280 + frameid * 4);
-}
-
-static void tegra_setup_frameidx(struct tegra_vde *vde,
- struct tegra_video_frame *frames,
- unsigned int frames_nb,
- u32 mbs_width, u32 mbs_height)
-{
- unsigned int idx;
-
- for (idx = 0; idx < frames_nb; idx++)
- tegra_vde_setup_frameid(vde, &frames[idx], idx,
- mbs_width, mbs_height);
-
- for (; idx < 17; idx++)
- tegra_vde_setup_frameid(vde, NULL, idx, 0, 0);
-}
-
-static void tegra_vde_setup_iram_entry(struct tegra_vde *vde,
- unsigned int table,
- unsigned int row,
- u32 value1, u32 value2)
-{
- u32 *iram_tables = vde->iram;
-
- trace_vde_setup_iram_entry(table, row, value1, value2);
-
- iram_tables[0x20 * table + row * 2 + 0] = value1;
- iram_tables[0x20 * table + row * 2 + 1] = value2;
-}
-
-static void tegra_vde_setup_iram_tables(struct tegra_vde *vde,
- struct tegra_video_frame *dpb_frames,
- unsigned int ref_frames_nb,
- unsigned int with_earlier_poc_nb)
-{
- struct tegra_video_frame *frame;
- int with_later_poc_nb;
- u32 value, aux_addr;
- unsigned int i, k;
-
- trace_vde_ref_l0(dpb_frames[0].frame_num);
-
- for (i = 0; i < 16; i++) {
- if (i < ref_frames_nb) {
- frame = &dpb_frames[i + 1];
-
- aux_addr = frame->aux_addr;
-
- value = (i + 1) << 26;
- value |= !(frame->flags & FLAG_B_FRAME) << 25;
- value |= 1 << 24;
- value |= frame->frame_num;
- } else {
- aux_addr = 0x6ADEAD00;
- value = 0x3f;
- }
-
- tegra_vde_setup_iram_entry(vde, 0, i, value, aux_addr);
- tegra_vde_setup_iram_entry(vde, 1, i, value, aux_addr);
- tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
- tegra_vde_setup_iram_entry(vde, 3, i, value, aux_addr);
- }
-
- if (!(dpb_frames[0].flags & FLAG_B_FRAME))
- return;
-
- if (with_earlier_poc_nb >= ref_frames_nb)
- return;
-
- with_later_poc_nb = ref_frames_nb - with_earlier_poc_nb;
-
- trace_vde_ref_l1(with_later_poc_nb, with_earlier_poc_nb);
-
- for (i = 0, k = with_earlier_poc_nb; i < with_later_poc_nb; i++, k++) {
- frame = &dpb_frames[k + 1];
-
- aux_addr = frame->aux_addr;
-
- value = (k + 1) << 26;
- value |= !(frame->flags & FLAG_B_FRAME) << 25;
- value |= 1 << 24;
- value |= frame->frame_num;
-
- tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
- }
-
- for (k = 0; i < ref_frames_nb; i++, k++) {
- frame = &dpb_frames[k + 1];
-
- aux_addr = frame->aux_addr;
-
- value = (k + 1) << 26;
- value |= !(frame->flags & FLAG_B_FRAME) << 25;
- value |= 1 << 24;
- value |= frame->frame_num;
-
- tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
- }
-}
-
-static int tegra_vde_setup_hw_context(struct tegra_vde *vde,
- struct tegra_vde_h264_decoder_ctx *ctx,
- struct tegra_video_frame *dpb_frames,
- dma_addr_t bitstream_data_addr,
- size_t bitstream_data_size,
- unsigned int macroblocks_nb)
-{
- struct device *dev = vde->dev;
- u32 value;
- int err;
-
- tegra_vde_set_bits(vde, 0x000A, vde->sxe, 0xF0);
- tegra_vde_set_bits(vde, 0x000B, vde->bsev, CMDQUE_CONTROL);
- tegra_vde_set_bits(vde, 0x8002, vde->mbe, 0x50);
- tegra_vde_set_bits(vde, 0x000A, vde->mbe, 0xA0);
- tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x14);
- tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x28);
- tegra_vde_set_bits(vde, 0x0A00, vde->mce, 0x08);
- tegra_vde_set_bits(vde, 0x000A, vde->tfe, 0x00);
- tegra_vde_set_bits(vde, 0x0005, vde->vdma, 0x04);
-
- tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x1C);
- tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x00);
- tegra_vde_writel(vde, 0x00000007, vde->vdma, 0x04);
- tegra_vde_writel(vde, 0x00000007, vde->frameid, 0x200);
- tegra_vde_writel(vde, 0x00000005, vde->tfe, 0x04);
- tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84);
- tegra_vde_writel(vde, 0x00000010, vde->sxe, 0x08);
- tegra_vde_writel(vde, 0x00000150, vde->sxe, 0x54);
- tegra_vde_writel(vde, 0x0000054C, vde->sxe, 0x58);
- tegra_vde_writel(vde, 0x00000E34, vde->sxe, 0x5C);
- tegra_vde_writel(vde, 0x063C063C, vde->mce, 0x10);
- tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS);
- tegra_vde_writel(vde, 0x0000150D, vde->bsev, BSE_CONFIG);
- tegra_vde_writel(vde, 0x00000100, vde->bsev, BSE_INT_ENB);
- tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x98);
- tegra_vde_writel(vde, 0x00000060, vde->bsev, 0x9C);
-
- memset(vde->iram + 128, 0, macroblocks_nb / 2);
-
- tegra_setup_frameidx(vde, dpb_frames, ctx->dpb_frames_nb,
- ctx->pic_width_in_mbs, ctx->pic_height_in_mbs);
-
- tegra_vde_setup_iram_tables(vde, dpb_frames,
- ctx->dpb_frames_nb - 1,
- ctx->dpb_ref_frames_with_earlier_poc_nb);
-
- /*
- * The IRAM mapping is write-combine, ensure that CPU buffers have
- * been flushed at this point.
- */
- wmb();
-
- tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x8C);
- tegra_vde_writel(vde, bitstream_data_addr + bitstream_data_size,
- vde->bsev, 0x54);
-
- vde->bitstream_data_addr = bitstream_data_addr;
-
- value = ctx->pic_width_in_mbs << 11 | ctx->pic_height_in_mbs << 3;
-
- tegra_vde_writel(vde, value, vde->bsev, 0x88);
-
- err = tegra_vde_wait_bsev(vde, false);
- if (err)
- return err;
-
- err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x800003FC, false);
- if (err)
- return err;
-
- value = 0x01500000;
- value |= ((vde->iram_lists_addr + 512) >> 2) & 0xFFFF;
-
- err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true);
- if (err)
- return err;
-
- err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x840F054C, false);
- if (err)
- return err;
-
- err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x80000080, false);
- if (err)
- return err;
-
- value = 0x0E340000 | ((vde->iram_lists_addr >> 2) & 0xFFFF);
-
- err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true);
- if (err)
- return err;
-
- value = 0x00800005;
- value |= ctx->pic_width_in_mbs << 11;
- value |= ctx->pic_height_in_mbs << 3;
-
- tegra_vde_writel(vde, value, vde->sxe, 0x10);
-
- value = !ctx->baseline_profile << 17;
- value |= ctx->level_idc << 13;
- value |= ctx->log2_max_pic_order_cnt_lsb << 7;
- value |= ctx->pic_order_cnt_type << 5;
- value |= ctx->log2_max_frame_num;
-
- tegra_vde_writel(vde, value, vde->sxe, 0x40);
-
- value = ctx->pic_init_qp << 25;
- value |= !!(ctx->deblocking_filter_control_present_flag) << 2;
- value |= !!ctx->pic_order_present_flag;
-
- tegra_vde_writel(vde, value, vde->sxe, 0x44);
-
- value = ctx->chroma_qp_index_offset;
- value |= ctx->num_ref_idx_l0_active_minus1 << 5;
- value |= ctx->num_ref_idx_l1_active_minus1 << 10;
- value |= !!ctx->constrained_intra_pred_flag << 15;
-
- tegra_vde_writel(vde, value, vde->sxe, 0x48);
-
- value = 0x0C000000;
- value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 24;
-
- tegra_vde_writel(vde, value, vde->sxe, 0x4C);
-
- value = 0x03800000;
- value |= bitstream_data_size & GENMASK(19, 15);
-
- tegra_vde_writel(vde, value, vde->sxe, 0x68);
-
- tegra_vde_writel(vde, bitstream_data_addr, vde->sxe, 0x6C);
-
- if (vde->soc->supports_ref_pic_marking)
- tegra_vde_writel(vde, vde->secure_bo->dma_addr, vde->sxe, 0x7c);
-
- value = 0x10000005;
- value |= ctx->pic_width_in_mbs << 11;
- value |= ctx->pic_height_in_mbs << 3;
-
- tegra_vde_writel(vde, value, vde->mbe, 0x80);
-
- value = 0x26800000;
- value |= ctx->level_idc << 4;
- value |= !ctx->baseline_profile << 1;
- value |= !!ctx->direct_8x8_inference_flag;
-
- tegra_vde_writel(vde, value, vde->mbe, 0x80);
-
- tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80);
- tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80);
- tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80);
-
- value = 0x20000000;
- value |= ctx->chroma_qp_index_offset << 8;
-
- tegra_vde_writel(vde, value, vde->mbe, 0x80);
-
- err = tegra_vde_setup_mbe_frame_idx(vde,
- ctx->dpb_frames_nb - 1,
- ctx->pic_order_cnt_type == 0);
- if (err) {
- dev_err(dev, "MBE frames setup failed %d\n", err);
- return err;
- }
-
- tegra_vde_mbe_set_0xa_reg(vde, 0, 0x000009FC);
- tegra_vde_mbe_set_0xa_reg(vde, 2, 0x61DEAD00);
- tegra_vde_mbe_set_0xa_reg(vde, 4, 0x62DEAD00);
- tegra_vde_mbe_set_0xa_reg(vde, 6, 0x63DEAD00);
- tegra_vde_mbe_set_0xa_reg(vde, 8, dpb_frames[0].aux_addr);
-
- value = 0xFC000000;
- value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 2;
-
- if (!ctx->baseline_profile)
- value |= !!(dpb_frames[0].flags & FLAG_REFERENCE) << 1;
-
- tegra_vde_writel(vde, value, vde->mbe, 0x80);
-
- err = tegra_vde_wait_mbe(vde);
- if (err) {
- dev_err(dev, "MBE programming failed %d\n", err);
- return err;
- }
-
- return 0;
-}
-
-static void tegra_vde_decode_frame(struct tegra_vde *vde,
- unsigned int macroblocks_nb)
-{
- reinit_completion(&vde->decode_completion);
-
- tegra_vde_writel(vde, 0x00000001, vde->bsev, 0x8C);
- tegra_vde_writel(vde, 0x20000000 | (macroblocks_nb - 1),
- vde->sxe, 0x00);
-}
-
-static int tegra_vde_validate_h264_ctx(struct device *dev,
- struct tegra_vde_h264_decoder_ctx *ctx)
-{
- if (ctx->dpb_frames_nb == 0 || ctx->dpb_frames_nb > 17) {
- dev_err(dev, "Bad DPB size %u\n", ctx->dpb_frames_nb);
- return -EINVAL;
- }
-
- if (ctx->level_idc > 15) {
- dev_err(dev, "Bad level value %u\n", ctx->level_idc);
- return -EINVAL;
- }
-
- if (ctx->pic_init_qp > 52) {
- dev_err(dev, "Bad pic_init_qp value %u\n", ctx->pic_init_qp);
- return -EINVAL;
- }
-
- if (ctx->log2_max_pic_order_cnt_lsb > 16) {
- dev_err(dev, "Bad log2_max_pic_order_cnt_lsb value %u\n",
- ctx->log2_max_pic_order_cnt_lsb);
- return -EINVAL;
- }
-
- if (ctx->log2_max_frame_num > 16) {
- dev_err(dev, "Bad log2_max_frame_num value %u\n",
- ctx->log2_max_frame_num);
- return -EINVAL;
- }
-
- if (ctx->chroma_qp_index_offset > 31) {
- dev_err(dev, "Bad chroma_qp_index_offset value %u\n",
- ctx->chroma_qp_index_offset);
- return -EINVAL;
- }
-
- if (ctx->pic_order_cnt_type > 2) {
- dev_err(dev, "Bad pic_order_cnt_type value %u\n",
- ctx->pic_order_cnt_type);
- return -EINVAL;
- }
-
- if (ctx->num_ref_idx_l0_active_minus1 > 15) {
- dev_err(dev, "Bad num_ref_idx_l0_active_minus1 value %u\n",
- ctx->num_ref_idx_l0_active_minus1);
- return -EINVAL;
- }
-
- if (ctx->num_ref_idx_l1_active_minus1 > 15) {
- dev_err(dev, "Bad num_ref_idx_l1_active_minus1 value %u\n",
- ctx->num_ref_idx_l1_active_minus1);
- return -EINVAL;
- }
-
- if (!ctx->pic_width_in_mbs || ctx->pic_width_in_mbs > 127) {
- dev_err(dev, "Bad pic_width_in_mbs value %u\n",
- ctx->pic_width_in_mbs);
- return -EINVAL;
- }
-
- if (!ctx->pic_height_in_mbs || ctx->pic_height_in_mbs > 127) {
- dev_err(dev, "Bad pic_height_in_mbs value %u\n",
- ctx->pic_height_in_mbs);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int tegra_vde_decode_begin(struct tegra_vde *vde,
- struct tegra_vde_h264_decoder_ctx *ctx,
- struct tegra_video_frame *dpb_frames,
- dma_addr_t bitstream_data_addr,
- size_t bitstream_data_size)
-{
- struct device *dev = vde->dev;
- unsigned int macroblocks_nb;
- int err;
-
- err = mutex_lock_interruptible(&vde->lock);
- if (err)
- return err;
-
- err = pm_runtime_resume_and_get(dev);
- if (err < 0)
- goto unlock;
-
- /*
- * We rely on the VDE registers reset value, otherwise VDE
- * causes bus lockup.
- */
- err = reset_control_assert(vde->rst_mc);
- if (err) {
- dev_err(dev, "DEC start: Failed to assert MC reset: %d\n",
- err);
- goto put_runtime_pm;
- }
-
- err = reset_control_reset(vde->rst);
- if (err) {
- dev_err(dev, "DEC start: Failed to reset HW: %d\n", err);
- goto put_runtime_pm;
- }
-
- err = reset_control_deassert(vde->rst_mc);
- if (err) {
- dev_err(dev, "DEC start: Failed to deassert MC reset: %d\n",
- err);
- goto put_runtime_pm;
- }
-
- macroblocks_nb = ctx->pic_width_in_mbs * ctx->pic_height_in_mbs;
-
- err = tegra_vde_setup_hw_context(vde, ctx, dpb_frames,
- bitstream_data_addr,
- bitstream_data_size,
- macroblocks_nb);
- if (err)
- goto put_runtime_pm;
-
- tegra_vde_decode_frame(vde, macroblocks_nb);
-
- return 0;
-
-put_runtime_pm:
- pm_runtime_mark_last_busy(dev);
- pm_runtime_put_autosuspend(dev);
-
-unlock:
- mutex_unlock(&vde->lock);
-
- return err;
-}
-
-static void tegra_vde_decode_abort(struct tegra_vde *vde)
-{
- struct device *dev = vde->dev;
- int err;
-
- /*
- * At first reset memory client to avoid resetting VDE HW in the
- * middle of DMA which could result into memory corruption or hang
- * the whole system.
- */
- err = reset_control_assert(vde->rst_mc);
- if (err)
- dev_err(dev, "DEC end: Failed to assert MC reset: %d\n", err);
-
- err = reset_control_assert(vde->rst);
- if (err)
- dev_err(dev, "DEC end: Failed to assert HW reset: %d\n", err);
-
- pm_runtime_mark_last_busy(dev);
- pm_runtime_put_autosuspend(dev);
-
- mutex_unlock(&vde->lock);
-}
-
-static int tegra_vde_decode_end(struct tegra_vde *vde)
-{
- unsigned int read_bytes, macroblocks_nb;
- struct device *dev = vde->dev;
- dma_addr_t bsev_ptr;
- long timeout;
- int ret;
-
- timeout = wait_for_completion_interruptible_timeout(
- &vde->decode_completion, msecs_to_jiffies(1000));
- if (timeout == 0) {
- bsev_ptr = tegra_vde_readl(vde, vde->bsev, 0x10);
- macroblocks_nb = tegra_vde_readl(vde, vde->sxe, 0xC8) & 0x1FFF;
- read_bytes = bsev_ptr ? bsev_ptr - vde->bitstream_data_addr : 0;
-
- dev_err(dev, "Decoding failed: read 0x%X bytes, %u macroblocks parsed\n",
- read_bytes, macroblocks_nb);
-
- ret = -EIO;
- } else if (timeout < 0) {
- ret = timeout;
- } else {
- ret = 0;
- }
-
- tegra_vde_decode_abort(vde);
-
- return ret;
-}
-
-static struct vb2_buffer *get_ref_buf(struct tegra_ctx *ctx,
- struct vb2_v4l2_buffer *dst,
- unsigned int dpb_idx)
-{
- const struct v4l2_h264_dpb_entry *dpb = ctx->h264.decode_params->dpb;
- struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q;
- int buf_idx = -1;
-
- if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
- buf_idx = vb2_find_timestamp(cap_q,
- dpb[dpb_idx].reference_ts, 0);
-
- /*
- * If a DPB entry is unused or invalid, address of current destination
- * buffer is returned.
- */
- if (buf_idx < 0)
- return &dst->vb2_buf;
-
- return vb2_get_buffer(cap_q, buf_idx);
-}
-
-static int tegra_vde_validate_vb_size(struct tegra_ctx *ctx,
- struct vb2_buffer *vb,
- unsigned int plane_id,
- size_t min_size)
-{
- u64 offset = vb->planes[plane_id].data_offset;
- struct device *dev = ctx->vde->dev;
-
- if (offset + min_size > vb2_plane_size(vb, plane_id)) {
- dev_err(dev, "Too small plane[%u] size %lu @0x%llX, should be at least %zu\n",
- plane_id, vb2_plane_size(vb, plane_id), offset, min_size);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int tegra_vde_h264_setup_frame(struct tegra_ctx *ctx,
- struct tegra_vde_h264_decoder_ctx *h264,
- struct v4l2_h264_reflist_builder *b,
- struct vb2_buffer *vb,
- unsigned int ref_id,
- unsigned int id)
-{
- struct v4l2_pix_format_mplane *pixfmt = &ctx->decoded_fmt.fmt.pix_mp;
- struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb);
- struct tegra_ctx_h264 *h = &ctx->h264;
- struct tegra_vde *vde = ctx->vde;
- struct device *dev = vde->dev;
- unsigned int cstride, lstride;
- unsigned int flags = 0;
- size_t lsize, csize;
- int err, frame_num;
-
- lsize = h264->pic_width_in_mbs * 16 * h264->pic_height_in_mbs * 16;
- csize = h264->pic_width_in_mbs * 8 * h264->pic_height_in_mbs * 8;
- lstride = pixfmt->plane_fmt[0].bytesperline;
- cstride = pixfmt->plane_fmt[1].bytesperline;
-
- err = tegra_vde_validate_vb_size(ctx, vb, 0, lsize);
- if (err)
- return err;
-
- err = tegra_vde_validate_vb_size(ctx, vb, 1, csize);
- if (err)
- return err;
-
- err = tegra_vde_validate_vb_size(ctx, vb, 2, csize);
- if (err)
- return err;
-
- if (!tb->aux || tb->aux->size < csize) {
- dev_err(dev, "Too small aux size %zd, should be at least %zu\n",
- tb->aux ? tb->aux->size : -1, csize);
- return -EINVAL;
- }
-
- if (id == 0) {
- frame_num = h->decode_params->frame_num;
-
- if (h->decode_params->nal_ref_idc)
- flags |= FLAG_REFERENCE;
- } else {
- frame_num = b->refs[ref_id].frame_num;
- }
-
- if (tb->b_frame)
- flags |= FLAG_B_FRAME;
-
- vde->frames[id].flags = flags;
- vde->frames[id].y_addr = tb->dma_addr[0];
- vde->frames[id].cb_addr = tb->dma_addr[1];
- vde->frames[id].cr_addr = tb->dma_addr[2];
- vde->frames[id].aux_addr = tb->aux->dma_addr;
- vde->frames[id].frame_num = frame_num & 0x7fffff;
- vde->frames[id].luma_atoms_pitch = lstride / VDE_ATOM;
- vde->frames[id].chroma_atoms_pitch = cstride / VDE_ATOM;
-
- return 0;
-}
-
-static int tegra_vde_h264_setup_frames(struct tegra_ctx *ctx,
- struct tegra_vde_h264_decoder_ctx *h264)
-{
- struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
- struct vb2_v4l2_buffer *dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
- const struct v4l2_h264_dpb_entry *dpb = ctx->h264.decode_params->dpb;
- struct tegra_m2m_buffer *tb = vb_to_tegra_buf(&dst->vb2_buf);
- struct tegra_ctx_h264 *h = &ctx->h264;
- struct v4l2_h264_reflist_builder b;
- struct h264_reflists reflists;
- struct vb2_buffer *ref;
- unsigned int i;
- u8 *dpb_id;
- int err;
-
- /*
- * Tegra hardware requires information about frame's type, assuming
- * that frame consists of the same type slices. Userspace must tag
- * frame's type appropriately.
- *
- * Decoding of a non-uniform frames isn't supported by hardware and
- * require software preprocessing that we don't implement. Decoding
- * is expected to fail in this case. Such video streams are rare in
- * practice, so not a big deal.
- *
- * If userspace doesn't tell us frame's type, then we will try decode
- * as-is.
- */
- v4l2_m2m_buf_copy_metadata(src, dst, true);
-
- if (h->decode_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BFRAME)
- tb->b_frame = true;
- else
- tb->b_frame = false;
-
- err = tegra_vde_h264_setup_frame(ctx, h264, NULL, &dst->vb2_buf, 0,
- h264->dpb_frames_nb++);
- if (err)
- return err;
-
- if (!(h->decode_params->flags & (V4L2_H264_DECODE_PARAM_FLAG_PFRAME |
- V4L2_H264_DECODE_PARAM_FLAG_BFRAME)))
- return 0;
-
- v4l2_h264_init_reflist_builder(&b, h->decode_params, h->sps, dpb);
-
- if (h->decode_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BFRAME) {
- v4l2_h264_build_b_ref_lists(&b, reflists.b0, reflists.b1);
- dpb_id = reflists.b0;
- } else {
- v4l2_h264_build_p_ref_list(&b, reflists.p);
- dpb_id = reflists.p;
- }
-
- for (i = 0; i < b.num_valid; i++) {
- ref = get_ref_buf(ctx, dst, dpb_id[i]);
-
- err = tegra_vde_h264_setup_frame(ctx, h264, &b, ref, dpb_id[i],
- h264->dpb_frames_nb++);
- if (err)
- return err;
-
- if (b.refs[dpb_id[i]].pic_order_count < b.cur_pic_order_count)
- h264->dpb_ref_frames_with_earlier_poc_nb++;
- }
-
- return 0;
-}
-
-static unsigned int to_tegra_vde_h264_level_idc(unsigned int level_idc)
-{
- switch (level_idc) {
- case 11:
- return 2;
- case 12:
- return 3;
- case 13:
- return 4;
- case 20:
- return 5;
- case 21:
- return 6;
- case 22:
- return 7;
- case 30:
- return 8;
- case 31:
- return 9;
- case 32:
- return 10;
- case 40:
- return 11;
- case 41:
- return 12;
- case 42:
- return 13;
- case 50:
- return 14;
- default:
- break;
- }
-
- return 15;
-}
-
-static int tegra_vde_h264_setup_context(struct tegra_ctx *ctx,
- struct tegra_vde_h264_decoder_ctx *h264)
-{
- struct tegra_ctx_h264 *h = &ctx->h264;
- struct tegra_vde *vde = ctx->vde;
- struct device *dev = vde->dev;
- int err;
-
- memset(h264, 0, sizeof(*h264));
- memset(vde->frames, 0, sizeof(vde->frames));
-
- tegra_vde_prepare_control_data(ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS);
- tegra_vde_prepare_control_data(ctx, V4L2_CID_STATELESS_H264_SPS);
- tegra_vde_prepare_control_data(ctx, V4L2_CID_STATELESS_H264_PPS);
-
- /* CABAC unsupported by hardware, requires software preprocessing */
- if (h->pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE)
- return -EOPNOTSUPP;
-
- if (h->sps->profile_idc == 66)
- h264->baseline_profile = 1;
-
- if (h->sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE)
- h264->direct_8x8_inference_flag = 1;
-
- if (h->pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED)
- h264->constrained_intra_pred_flag = 1;
-
- if (h->pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT)
- h264->deblocking_filter_control_present_flag = 1;
-
- if (h->pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT)
- h264->pic_order_present_flag = 1;
-
- h264->level_idc = to_tegra_vde_h264_level_idc(h->sps->level_idc);
- h264->log2_max_pic_order_cnt_lsb = h->sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
- h264->log2_max_frame_num = h->sps->log2_max_frame_num_minus4 + 4;
- h264->pic_order_cnt_type = h->sps->pic_order_cnt_type;
- h264->pic_width_in_mbs = h->sps->pic_width_in_mbs_minus1 + 1;
- h264->pic_height_in_mbs = h->sps->pic_height_in_map_units_minus1 + 1;
-
- h264->num_ref_idx_l0_active_minus1 = h->pps->num_ref_idx_l0_default_active_minus1;
- h264->num_ref_idx_l1_active_minus1 = h->pps->num_ref_idx_l1_default_active_minus1;
- h264->chroma_qp_index_offset = h->pps->chroma_qp_index_offset & 0x1f;
- h264->pic_init_qp = h->pps->pic_init_qp_minus26 + 26;
-
- err = tegra_vde_h264_setup_frames(ctx, h264);
- if (err)
- return err;
-
- err = tegra_vde_validate_h264_ctx(dev, h264);
- if (err)
- return err;
-
- return 0;
-}
-
-int tegra_vde_h264_decode_run(struct tegra_ctx *ctx)
-{
- struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
- struct tegra_m2m_buffer *bitstream = vb_to_tegra_buf(&src->vb2_buf);
- size_t bitstream_size = vb2_get_plane_payload(&src->vb2_buf, 0);
- struct tegra_vde_h264_decoder_ctx h264;
- struct tegra_vde *vde = ctx->vde;
- int err;
-
- err = tegra_vde_h264_setup_context(ctx, &h264);
- if (err)
- return err;
-
- err = tegra_vde_decode_begin(vde, &h264, vde->frames,
- bitstream->dma_addr[0],
- bitstream_size);
- if (err)
- return err;
-
- return 0;
-}
-
-int tegra_vde_h264_decode_wait(struct tegra_ctx *ctx)
-{
- return tegra_vde_decode_end(ctx->vde);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * NVIDIA Tegra Video decoder driver
- *
- * Copyright (C) 2016-2019 GRATE-DRIVER project
- */
-
-#include <linux/iommu.h>
-#include <linux/iova.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-
-#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
-#include <asm/dma-iommu.h>
-#endif
-
-#include "vde.h"
-
-int tegra_vde_iommu_map(struct tegra_vde *vde,
- struct sg_table *sgt,
- struct iova **iovap,
- size_t size)
-{
- struct iova *iova;
- unsigned long shift;
- unsigned long end;
- dma_addr_t addr;
-
- end = vde->domain->geometry.aperture_end;
- size = iova_align(&vde->iova, size);
- shift = iova_shift(&vde->iova);
-
- iova = alloc_iova(&vde->iova, size >> shift, end >> shift, true);
- if (!iova)
- return -ENOMEM;
-
- addr = iova_dma_addr(&vde->iova, iova);
-
- size = iommu_map_sgtable(vde->domain, addr, sgt,
- IOMMU_READ | IOMMU_WRITE);
- if (!size) {
- __free_iova(&vde->iova, iova);
- return -ENXIO;
- }
-
- *iovap = iova;
-
- return 0;
-}
-
-void tegra_vde_iommu_unmap(struct tegra_vde *vde, struct iova *iova)
-{
- unsigned long shift = iova_shift(&vde->iova);
- unsigned long size = iova_size(iova) << shift;
- dma_addr_t addr = iova_dma_addr(&vde->iova, iova);
-
- iommu_unmap(vde->domain, addr, size);
- __free_iova(&vde->iova, iova);
-}
-
-int tegra_vde_iommu_init(struct tegra_vde *vde)
-{
- struct device *dev = vde->dev;
- struct iova *iova;
- unsigned long order;
- unsigned long shift;
- int err;
-
- vde->group = iommu_group_get(dev);
- if (!vde->group)
- return 0;
-
-#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
- if (dev->archdata.mapping) {
- struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
-
- arm_iommu_detach_device(dev);
- arm_iommu_release_mapping(mapping);
- }
-#endif
- vde->domain = iommu_domain_alloc(&platform_bus_type);
- if (!vde->domain) {
- err = -ENOMEM;
- goto put_group;
- }
-
- err = iova_cache_get();
- if (err)
- goto free_domain;
-
- order = __ffs(vde->domain->pgsize_bitmap);
- init_iova_domain(&vde->iova, 1UL << order, 0);
-
- err = iommu_attach_group(vde->domain, vde->group);
- if (err)
- goto put_iova;
-
- /*
- * We're using some static addresses that are not accessible by VDE
- * to trap invalid memory accesses.
- */
- shift = iova_shift(&vde->iova);
- iova = reserve_iova(&vde->iova, 0x60000000 >> shift,
- 0x70000000 >> shift);
- if (!iova) {
- err = -ENOMEM;
- goto detach_group;
- }
-
- vde->iova_resv_static_addresses = iova;
-
- /*
- * BSEV's end-address wraps around due to integer overflow during
- * of hardware context preparation if IOVA is allocated at the end
- * of address space and VDE can't handle that. Hence simply reserve
- * the last page to avoid the problem.
- */
- iova = reserve_iova(&vde->iova, 0xffffffff >> shift,
- (0xffffffff >> shift) + 1);
- if (!iova) {
- err = -ENOMEM;
- goto unreserve_iova;
- }
-
- vde->iova_resv_last_page = iova;
-
- return 0;
-
-unreserve_iova:
- __free_iova(&vde->iova, vde->iova_resv_static_addresses);
-detach_group:
- iommu_detach_group(vde->domain, vde->group);
-put_iova:
- put_iova_domain(&vde->iova);
- iova_cache_put();
-free_domain:
- iommu_domain_free(vde->domain);
-put_group:
- iommu_group_put(vde->group);
-
- return err;
-}
-
-void tegra_vde_iommu_deinit(struct tegra_vde *vde)
-{
- if (vde->domain) {
- __free_iova(&vde->iova, vde->iova_resv_last_page);
- __free_iova(&vde->iova, vde->iova_resv_static_addresses);
- iommu_detach_group(vde->domain, vde->group);
- put_iova_domain(&vde->iova);
- iova_cache_put();
- iommu_domain_free(vde->domain);
- iommu_group_put(vde->group);
-
- vde->domain = NULL;
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#undef TRACE_SYSTEM
-#define TRACE_SYSTEM tegra_vde
-
-#if !defined(TEGRA_VDE_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
-#define TEGRA_VDE_TRACE_H
-
-#include <linux/tracepoint.h>
-
-#include "vde.h"
-
-DECLARE_EVENT_CLASS(register_access,
- TP_PROTO(struct tegra_vde *vde, void __iomem *base,
- u32 offset, u32 value),
- TP_ARGS(vde, base, offset, value),
- TP_STRUCT__entry(
- __string(hw_name, tegra_vde_reg_base_name(vde, base))
- __field(u32, offset)
- __field(u32, value)
- ),
- TP_fast_assign(
- __assign_str(hw_name, tegra_vde_reg_base_name(vde, base));
- __entry->offset = offset;
- __entry->value = value;
- ),
- TP_printk("%s:0x%03x 0x%08x", __get_str(hw_name), __entry->offset,
- __entry->value)
-);
-
-DEFINE_EVENT(register_access, vde_writel,
- TP_PROTO(struct tegra_vde *vde, void __iomem *base,
- u32 offset, u32 value),
- TP_ARGS(vde, base, offset, value));
-DEFINE_EVENT(register_access, vde_readl,
- TP_PROTO(struct tegra_vde *vde, void __iomem *base,
- u32 offset, u32 value),
- TP_ARGS(vde, base, offset, value));
-
-TRACE_EVENT(vde_setup_iram_entry,
- TP_PROTO(unsigned int table, unsigned int row, u32 value, u32 aux_addr),
- TP_ARGS(table, row, value, aux_addr),
- TP_STRUCT__entry(
- __field(unsigned int, table)
- __field(unsigned int, row)
- __field(u32, value)
- __field(u32, aux_addr)
- ),
- TP_fast_assign(
- __entry->table = table;
- __entry->row = row;
- __entry->value = value;
- __entry->aux_addr = aux_addr;
- ),
- TP_printk("[%u][%u] = { 0x%08x (flags = \"%s\", frame_num = %u); 0x%08x }",
- __entry->table, __entry->row, __entry->value,
- __print_flags(__entry->value, " ", { (1 << 25), "B" }),
- __entry->value & 0x7FFFFF, __entry->aux_addr)
-);
-
-TRACE_EVENT(vde_ref_l0,
- TP_PROTO(unsigned int frame_num),
- TP_ARGS(frame_num),
- TP_STRUCT__entry(
- __field(unsigned int, frame_num)
- ),
- TP_fast_assign(
- __entry->frame_num = frame_num;
- ),
- TP_printk("REF L0: DPB: Frame 0: frame_num = %u", __entry->frame_num)
-);
-
-TRACE_EVENT(vde_ref_l1,
- TP_PROTO(unsigned int with_later_poc_nb,
- unsigned int with_earlier_poc_nb),
- TP_ARGS(with_later_poc_nb, with_earlier_poc_nb),
- TP_STRUCT__entry(
- __field(unsigned int, with_later_poc_nb)
- __field(unsigned int, with_earlier_poc_nb)
- ),
- TP_fast_assign(
- __entry->with_later_poc_nb = with_later_poc_nb;
- __entry->with_earlier_poc_nb = with_earlier_poc_nb;
- ),
- TP_printk("REF L1: with_later_poc_nb %u, with_earlier_poc_nb %u",
- __entry->with_later_poc_nb, __entry->with_earlier_poc_nb)
-);
-
-#endif /* TEGRA_VDE_TRACE_H */
-
-/* This part must be outside protection */
-#undef TRACE_INCLUDE_PATH
-#define TRACE_INCLUDE_PATH ../../drivers/media/platform/tegra/vde
-#define TRACE_INCLUDE_FILE trace
-#include <trace/define_trace.h>
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * NVIDIA Tegra Video decoder driver
- *
- * Copyright (C) 2019-2022 Dmitry Osipenko <digetx@gmail.com>
- *
- * Based on Cedrus driver by Bootlin.
- * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
- * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
- *
- * Based on Rockchip driver by Collabora.
- * Copyright (C) 2019 Boris Brezillon <boris.brezillon@collabora.com>
- */
-
-#include <linux/err.h>
-#include <linux/slab.h>
-
-#include "vde.h"
-
-static const struct v4l2_ctrl_config ctrl_cfgs[] = {
- { .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, },
- { .id = V4L2_CID_STATELESS_H264_SPS, },
- { .id = V4L2_CID_STATELESS_H264_PPS, },
- {
- .id = V4L2_CID_STATELESS_H264_DECODE_MODE,
- .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
- .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
- .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
- },
- {
- .id = V4L2_CID_STATELESS_H264_START_CODE,
- .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
- .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
- .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
- },
- {
- .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
- .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
- .max = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
- .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
- },
- {
- .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL,
- .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
- .max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
- },
-};
-
-static inline struct tegra_ctx *fh_to_tegra_ctx(struct v4l2_fh *fh)
-{
- return container_of(fh, struct tegra_ctx, fh);
-}
-
-static void tegra_set_control_data(struct tegra_ctx *ctx, void *data, u32 id)
-{
- switch (id) {
- case V4L2_CID_STATELESS_H264_DECODE_PARAMS:
- ctx->h264.decode_params = data;
- break;
- case V4L2_CID_STATELESS_H264_SPS:
- ctx->h264.sps = data;
- break;
- case V4L2_CID_STATELESS_H264_PPS:
- ctx->h264.pps = data;
- break;
- }
-}
-
-void tegra_vde_prepare_control_data(struct tegra_ctx *ctx, u32 id)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(ctrl_cfgs); i++) {
- if (ctx->ctrls[i]->id == id) {
- tegra_set_control_data(ctx, ctx->ctrls[i]->p_cur.p, id);
- return;
- }
- }
-
- tegra_set_control_data(ctx, NULL, id);
-}
-
-static int tegra_queue_setup(struct vb2_queue *vq,
- unsigned int *nbufs,
- unsigned int *num_planes,
- unsigned int sizes[],
- struct device *alloc_devs[])
-{
- struct tegra_ctx *ctx = vb2_get_drv_priv(vq);
- struct v4l2_format *f;
- unsigned int i;
-
- if (V4L2_TYPE_IS_OUTPUT(vq->type))
- f = &ctx->coded_fmt;
- else
- f = &ctx->decoded_fmt;
-
- if (*num_planes) {
- if (*num_planes != f->fmt.pix_mp.num_planes)
- return -EINVAL;
-
- for (i = 0; i < f->fmt.pix_mp.num_planes; i++) {
- if (sizes[i] < f->fmt.pix_mp.plane_fmt[i].sizeimage)
- return -EINVAL;
- }
- } else {
- *num_planes = f->fmt.pix_mp.num_planes;
-
- for (i = 0; i < f->fmt.pix_mp.num_planes; i++)
- sizes[i] = f->fmt.pix_mp.plane_fmt[i].sizeimage;
- }
-
- return 0;
-}
-
-static int tegra_buf_out_validate(struct vb2_buffer *vb)
-{
- struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
-
- vbuf->field = V4L2_FIELD_NONE;
- return 0;
-}
-
-static void __tegra_buf_cleanup(struct vb2_buffer *vb, unsigned int i)
-{
- struct vb2_queue *vq = vb->vb2_queue;
- struct tegra_ctx *ctx = vb2_get_drv_priv(vq);
- struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb);
-
- while (i--) {
- if (tb->a[i]) {
- tegra_vde_dmabuf_cache_unmap(ctx->vde, tb->a[i], true);
- tb->a[i] = NULL;
- }
-
- if (tb->iova[i]) {
- tegra_vde_iommu_unmap(ctx->vde, tb->iova[i]);
- tb->iova[i] = NULL;
- }
- }
-
- if (tb->aux) {
- tegra_vde_free_bo(tb->aux);
- tb->aux = NULL;
- }
-}
-
-static int tegra_buf_init(struct vb2_buffer *vb)
-{
- struct vb2_queue *vq = vb->vb2_queue;
- struct tegra_ctx *ctx = vb2_get_drv_priv(vq);
- struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb);
- struct tegra_vde *vde = ctx->vde;
- enum dma_data_direction dma_dir;
- struct sg_table *sgt;
- unsigned int i;
- int err;
-
- if (V4L2_TYPE_IS_CAPTURE(vq->type) && vb->num_planes > 1) {
- /*
- * Tegra decoder writes auxiliary data for I/P frames.
- * This data is needed for decoding of B frames.
- */
- err = tegra_vde_alloc_bo(vde, &tb->aux, DMA_FROM_DEVICE,
- vb2_plane_size(vb, 1));
- if (err)
- return err;
- }
-
- if (V4L2_TYPE_IS_OUTPUT(vq->type))
- dma_dir = DMA_TO_DEVICE;
- else
- dma_dir = DMA_FROM_DEVICE;
-
- for (i = 0; i < vb->num_planes; i++) {
- if (vq->memory == VB2_MEMORY_DMABUF) {
- get_dma_buf(vb->planes[i].dbuf);
-
- err = tegra_vde_dmabuf_cache_map(vde, vb->planes[i].dbuf,
- dma_dir, &tb->a[i],
- &tb->dma_base[i]);
- if (err) {
- dma_buf_put(vb->planes[i].dbuf);
- goto cleanup;
- }
-
- continue;
- }
-
- if (vde->domain) {
- sgt = vb2_dma_sg_plane_desc(vb, i);
-
- err = tegra_vde_iommu_map(vde, sgt, &tb->iova[i],
- vb2_plane_size(vb, i));
- if (err)
- goto cleanup;
-
- tb->dma_base[i] = iova_dma_addr(&vde->iova, tb->iova[i]);
- } else {
- tb->dma_base[i] = vb2_dma_contig_plane_dma_addr(vb, i);
- }
- }
-
- return 0;
-
-cleanup:
- __tegra_buf_cleanup(vb, i);
-
- return err;
-}
-
-static void tegra_buf_cleanup(struct vb2_buffer *vb)
-{
- __tegra_buf_cleanup(vb, vb->num_planes);
-}
-
-static int tegra_buf_prepare(struct vb2_buffer *vb)
-{
- struct vb2_queue *vq = vb->vb2_queue;
- struct tegra_ctx *ctx = vb2_get_drv_priv(vq);
- struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb);
- size_t hw_align, hw_size, hw_payload, size, offset;
- struct v4l2_pix_format_mplane *pixfmt;
- unsigned int i;
- void *vb_data;
-
- if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
- hw_align = BSEV_ALIGN;
- pixfmt = &ctx->coded_fmt.fmt.pix_mp;
- } else {
- hw_align = FRAMEID_ALIGN;
- pixfmt = &ctx->decoded_fmt.fmt.pix_mp;
- }
-
- for (i = 0; i < vb->num_planes; i++) {
- offset = vb->planes[i].data_offset;
-
- if (offset & (hw_align - 1))
- return -EINVAL;
-
- if (V4L2_TYPE_IS_CAPTURE(vq->type)) {
- size = pixfmt->plane_fmt[i].sizeimage;
- hw_payload = ALIGN(size, VDE_ATOM);
- } else {
- size = vb2_get_plane_payload(vb, i) - offset;
- hw_payload = ALIGN(size + VDE_ATOM, SXE_BUFFER);
- }
-
- hw_size = offset + hw_payload;
-
- if (vb2_plane_size(vb, i) < hw_size)
- return -EINVAL;
-
- vb2_set_plane_payload(vb, i, hw_payload);
-
- if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
- vb_data = vb2_plane_vaddr(vb, i);
-
- /*
- * Hardware requires zero-padding of coded data.
- * Otherwise it will fail to parse the trailing
- * data and abort the decoding.
- */
- if (vb_data)
- memset(vb_data + offset + size, 0,
- hw_size - offset - size);
- }
-
- tb->dma_addr[i] = tb->dma_base[i] + offset;
- }
-
- switch (pixfmt->pixelformat) {
- case V4L2_PIX_FMT_YVU420M:
- swap(tb->dma_addr[1], tb->dma_addr[2]);
- break;
- }
-
- return 0;
-}
-
-static void tegra_buf_queue(struct vb2_buffer *vb)
-{
- struct tegra_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
- struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
-
- v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
-}
-
-static void tegra_buf_request_complete(struct vb2_buffer *vb)
-{
- struct tegra_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
-
- v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->hdl);
-}
-
-static int tegra_start_streaming(struct vb2_queue *vq, unsigned int count)
-{
- return 0;
-}
-
-static void tegra_stop_streaming(struct vb2_queue *vq)
-{
- struct tegra_ctx *ctx = vb2_get_drv_priv(vq);
-
- while (true) {
- struct vb2_v4l2_buffer *vbuf;
-
- if (V4L2_TYPE_IS_OUTPUT(vq->type))
- vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
- else
- vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
-
- if (!vbuf)
- break;
-
- v4l2_ctrl_request_complete(vbuf->vb2_buf.req_obj.req, &ctx->hdl);
- v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
- }
-}
-
-static const struct vb2_ops tegra_qops = {
- .queue_setup = tegra_queue_setup,
- .buf_init = tegra_buf_init,
- .buf_cleanup = tegra_buf_cleanup,
- .buf_prepare = tegra_buf_prepare,
- .buf_queue = tegra_buf_queue,
- .buf_out_validate = tegra_buf_out_validate,
- .buf_request_complete = tegra_buf_request_complete,
- .start_streaming = tegra_start_streaming,
- .stop_streaming = tegra_stop_streaming,
- .wait_prepare = vb2_ops_wait_prepare,
- .wait_finish = vb2_ops_wait_finish,
-};
-
-static int tegra_queue_init(void *priv,
- struct vb2_queue *src_vq,
- struct vb2_queue *dst_vq)
-{
- struct tegra_ctx *ctx = priv;
- struct tegra_vde *vde = ctx->vde;
- const struct vb2_mem_ops *mem_ops;
- unsigned long dma_attrs;
- int err;
-
- /*
- * TODO: Switch to use of vb2_dma_contig_memops uniformly once we
- * will add IOMMU_DOMAIN support for video decoder to tegra-smmu
- * driver. For now we need to stick with SG ops in order to be able
- * to get SGT table easily. This is suboptimal since SG mappings are
- * wasting CPU cache and we don't need that caching.
- */
- if (vde->domain)
- mem_ops = &vb2_dma_sg_memops;
- else
- mem_ops = &vb2_dma_contig_memops;
-
- dma_attrs = DMA_ATTR_WRITE_COMBINE;
-
- src_vq->buf_struct_size = sizeof(struct tegra_m2m_buffer);
- src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
- src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
- src_vq->io_modes = VB2_DMABUF | VB2_MMAP;
- src_vq->supports_requests = true;
- src_vq->requires_requests = true;
- src_vq->lock = &vde->v4l2_lock;
- src_vq->dma_attrs = dma_attrs;
- src_vq->mem_ops = mem_ops;
- src_vq->ops = &tegra_qops;
- src_vq->drv_priv = ctx;
- src_vq->dev = vde->dev;
-
- err = vb2_queue_init(src_vq);
- if (err) {
- v4l2_err(&vde->v4l2_dev,
- "failed to initialize src queue: %d\n", err);
- return err;
- }
-
- /*
- * We may need to zero the end of bitstream in kernel if userspace
- * doesn't do that, hence kmap is needed for the coded data. It's not
- * needed for framebuffers.
- */
- dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
-
- dst_vq->buf_struct_size = sizeof(struct tegra_m2m_buffer);
- dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
- dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
- dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
- dst_vq->lock = &vde->v4l2_lock;
- dst_vq->dma_attrs = dma_attrs;
- dst_vq->mem_ops = mem_ops;
- dst_vq->ops = &tegra_qops;
- dst_vq->drv_priv = ctx;
- dst_vq->dev = vde->dev;
-
- err = vb2_queue_init(dst_vq);
- if (err) {
- v4l2_err(&vde->v4l2_dev,
- "failed to initialize dst queue: %d\n", err);
- return err;
- }
-
- return 0;
-}
-
-static void tegra_reset_fmt(struct tegra_ctx *ctx, struct v4l2_format *f,
- u32 fourcc)
-{
- memset(f, 0, sizeof(*f));
- f->fmt.pix_mp.pixelformat = fourcc;
- f->fmt.pix_mp.field = V4L2_FIELD_NONE;
- f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT;
- f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
- f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709;
- f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
-}
-
-static void tegra_reset_coded_fmt(struct tegra_ctx *ctx)
-{
- const struct tegra_vde_soc *soc = ctx->vde->soc;
- struct v4l2_format *f = &ctx->coded_fmt;
-
- ctx->coded_fmt_desc = &soc->coded_fmts[0];
- tegra_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc);
-
- f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
- f->fmt.pix_mp.width = ctx->coded_fmt_desc->frmsize.min_width;
- f->fmt.pix_mp.height = ctx->coded_fmt_desc->frmsize.min_height;
-}
-
-static void tegra_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
- u32 pixelformat, u32 width, u32 height)
-{
- const struct v4l2_format_info *info = v4l2_format_info(pixelformat);
- struct v4l2_plane_pix_format *plane;
- unsigned int i;
-
- switch (pixelformat) {
- case V4L2_PIX_FMT_YUV420M:
- case V4L2_PIX_FMT_YVU420M:
- pixfmt->width = width;
- pixfmt->height = height;
- pixfmt->pixelformat = pixelformat;
- pixfmt->num_planes = info->mem_planes;
-
- for (i = 0; i < pixfmt->num_planes; i++) {
- unsigned int hdiv = (i == 0) ? 1 : 2;
- unsigned int vdiv = (i == 0) ? 1 : 2;
-
- /*
- * VDE is connected to Graphics Memory using 128bit port,
- * all memory accesses are made using 16B atoms.
- *
- * V4L requires Cb/Cr strides to be exactly half of the
- * Y stride, hence we're aligning Y to 16B x 2.
- */
- plane = &pixfmt->plane_fmt[i];
- plane->bytesperline = ALIGN(width, VDE_ATOM * 2) / hdiv;
- plane->sizeimage = plane->bytesperline * height / vdiv;
- }
-
- break;
- }
-}
-
-static void tegra_reset_decoded_fmt(struct tegra_ctx *ctx)
-{
- struct v4l2_format *f = &ctx->decoded_fmt;
-
- tegra_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
- f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
- tegra_fill_pixfmt_mp(&f->fmt.pix_mp,
- ctx->coded_fmt_desc->decoded_fmts[0],
- ctx->coded_fmt.fmt.pix_mp.width,
- ctx->coded_fmt.fmt.pix_mp.height);
-}
-
-static void tegra_job_finish(struct tegra_ctx *ctx,
- enum vb2_buffer_state result)
-{
- v4l2_m2m_buf_done_and_job_finish(ctx->vde->m2m, ctx->fh.m2m_ctx,
- result);
-}
-
-static void tegra_decode_complete(struct work_struct *work)
-{
- struct tegra_ctx *ctx = container_of(work, struct tegra_ctx, work);
- int err;
-
- err = ctx->coded_fmt_desc->decode_wait(ctx);
- if (err)
- tegra_job_finish(ctx, VB2_BUF_STATE_ERROR);
- else
- tegra_job_finish(ctx, VB2_BUF_STATE_DONE);
-}
-
-static int tegra_querycap(struct file *file, void *priv,
- struct v4l2_capability *cap)
-{
- strscpy(cap->bus_info, "platform:tegra-vde", sizeof(cap->bus_info));
- strscpy(cap->driver, "tegra-vde", sizeof(cap->driver));
- strscpy(cap->card, "tegra-vde", sizeof(cap->card));
-
- return 0;
-}
-
-static int tegra_enum_decoded_fmt(struct file *file, void *priv,
- struct v4l2_fmtdesc *f)
-{
- struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
-
- if (WARN_ON(!ctx->coded_fmt_desc))
- return -EINVAL;
-
- if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts)
- return -EINVAL;
-
- f->pixelformat = ctx->coded_fmt_desc->decoded_fmts[f->index];
-
- return 0;
-}
-
-static int tegra_g_decoded_fmt(struct file *file, void *priv,
- struct v4l2_format *f)
-{
- struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
-
- *f = ctx->decoded_fmt;
- return 0;
-}
-
-static int tegra_try_decoded_fmt(struct file *file, void *priv,
- struct v4l2_format *f)
-{
- struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
- struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
- const struct tegra_coded_fmt_desc *coded_desc;
- unsigned int i;
-
- /*
- * The codec context should point to a coded format desc, if the format
- * on the coded end has not been set yet, it should point to the
- * default value.
- */
- coded_desc = ctx->coded_fmt_desc;
- if (WARN_ON(!coded_desc))
- return -EINVAL;
-
- if (!coded_desc->num_decoded_fmts)
- return -EINVAL;
-
- for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
- if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
- break;
- }
-
- if (i == coded_desc->num_decoded_fmts)
- pix_mp->pixelformat = coded_desc->decoded_fmts[0];
-
- /* always apply the frmsize constraint of the coded end */
- v4l2_apply_frmsize_constraints(&pix_mp->width,
- &pix_mp->height,
- &coded_desc->frmsize);
-
- tegra_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
- pix_mp->width, pix_mp->height);
- pix_mp->field = V4L2_FIELD_NONE;
-
- return 0;
-}
-
-static int tegra_s_decoded_fmt(struct file *file, void *priv,
- struct v4l2_format *f)
-{
- struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
- struct vb2_queue *vq;
- int err;
-
- /* change not allowed if queue is busy */
- vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
- V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
- if (vb2_is_busy(vq))
- return -EBUSY;
-
- err = tegra_try_decoded_fmt(file, priv, f);
- if (err)
- return err;
-
- ctx->decoded_fmt = *f;
-
- return 0;
-}
-
-static int tegra_enum_coded_fmt(struct file *file, void *priv,
- struct v4l2_fmtdesc *f)
-{
- struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
- const struct tegra_vde_soc *soc = ctx->vde->soc;
-
- if (f->index >= soc->num_coded_fmts)
- return -EINVAL;
-
- f->pixelformat = soc->coded_fmts[f->index].fourcc;
-
- return 0;
-}
-
-static int tegra_g_coded_fmt(struct file *file, void *priv,
- struct v4l2_format *f)
-{
- struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
-
- *f = ctx->coded_fmt;
- return 0;
-}
-
-static const struct tegra_coded_fmt_desc *
-tegra_find_coded_fmt_desc(struct tegra_ctx *ctx, u32 fourcc)
-{
- const struct tegra_vde_soc *soc = ctx->vde->soc;
- unsigned int i;
-
- for (i = 0; i < soc->num_coded_fmts; i++) {
- if (soc->coded_fmts[i].fourcc == fourcc)
- return &soc->coded_fmts[i];
- }
-
- return NULL;
-}
-
-static int tegra_try_coded_fmt(struct file *file, void *priv,
- struct v4l2_format *f)
-{
- struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
- struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
- const struct tegra_vde_soc *soc = ctx->vde->soc;
- int size = pix_mp->plane_fmt[0].sizeimage;
- const struct tegra_coded_fmt_desc *desc;
-
- desc = tegra_find_coded_fmt_desc(ctx, pix_mp->pixelformat);
- if (!desc) {
- pix_mp->pixelformat = soc->coded_fmts[0].fourcc;
- desc = &soc->coded_fmts[0];
- }
-
- v4l2_apply_frmsize_constraints(&pix_mp->width,
- &pix_mp->height,
- &desc->frmsize);
-
- pix_mp->plane_fmt[0].sizeimage = max(ALIGN(size, SXE_BUFFER), SZ_2M);
- pix_mp->field = V4L2_FIELD_NONE;
- pix_mp->num_planes = 1;
-
- return 0;
-}
-
-static int tegra_s_coded_fmt(struct file *file, void *priv,
- struct v4l2_format *f)
-{
- struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
- struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
- const struct tegra_coded_fmt_desc *desc;
- struct vb2_queue *peer_vq, *vq;
- struct v4l2_format *cap_fmt;
- int err;
-
- /*
- * In order to support dynamic resolution change, the decoder admits
- * a resolution change, as long as the pixelformat remains. Can't be
- * done if streaming.
- */
- vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
- if (vb2_is_streaming(vq) ||
- (vb2_is_busy(vq) &&
- f->fmt.pix_mp.pixelformat != ctx->coded_fmt.fmt.pix_mp.pixelformat))
- return -EBUSY;
-
- /*
- * Since format change on the OUTPUT queue will reset the CAPTURE
- * queue, we can't allow doing so when the CAPTURE queue has buffers
- * allocated.
- */
- peer_vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
- if (vb2_is_busy(peer_vq))
- return -EBUSY;
-
- err = tegra_try_coded_fmt(file, priv, f);
- if (err)
- return err;
-
- desc = tegra_find_coded_fmt_desc(ctx, f->fmt.pix_mp.pixelformat);
- if (!desc)
- return -EINVAL;
-
- ctx->coded_fmt_desc = desc;
- ctx->coded_fmt = *f;
-
- /*
- * Current decoded format might have become invalid with newly
- * selected codec, so reset it to default just to be safe and
- * keep internal driver state sane. User is mandated to set
- * the decoded format again after we return, so we don't need
- * anything smarter.
- *
- * Note that this will propagates any size changes to the decoded format.
- */
- tegra_reset_decoded_fmt(ctx);
-
- /* propagate colorspace information to capture */
- cap_fmt = &ctx->decoded_fmt;
- cap_fmt->fmt.pix_mp.xfer_func = f->fmt.pix_mp.xfer_func;
- cap_fmt->fmt.pix_mp.ycbcr_enc = f->fmt.pix_mp.ycbcr_enc;
- cap_fmt->fmt.pix_mp.colorspace = f->fmt.pix_mp.colorspace;
- cap_fmt->fmt.pix_mp.quantization = f->fmt.pix_mp.quantization;
-
- return 0;
-}
-
-static int tegra_enum_framesizes(struct file *file, void *priv,
- struct v4l2_frmsizeenum *fsize)
-{
- struct tegra_ctx *ctx = fh_to_tegra_ctx(priv);
- const struct tegra_coded_fmt_desc *fmt;
-
- if (fsize->index)
- return -EINVAL;
-
- fmt = tegra_find_coded_fmt_desc(ctx, fsize->pixel_format);
- if (!fmt)
- return -EINVAL;
-
- fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
- fsize->stepwise = fmt->frmsize;
-
- return 0;
-}
-
-static const struct v4l2_ioctl_ops tegra_v4l2_ioctl_ops = {
- .vidioc_querycap = tegra_querycap,
- .vidioc_enum_framesizes = tegra_enum_framesizes,
-
- .vidioc_try_fmt_vid_out_mplane = tegra_try_coded_fmt,
- .vidioc_g_fmt_vid_out_mplane = tegra_g_coded_fmt,
- .vidioc_s_fmt_vid_out_mplane = tegra_s_coded_fmt,
- .vidioc_enum_fmt_vid_out = tegra_enum_coded_fmt,
-
- .vidioc_try_fmt_vid_cap_mplane = tegra_try_decoded_fmt,
- .vidioc_g_fmt_vid_cap_mplane = tegra_g_decoded_fmt,
- .vidioc_s_fmt_vid_cap_mplane = tegra_s_decoded_fmt,
- .vidioc_enum_fmt_vid_cap = tegra_enum_decoded_fmt,
-
- .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
- .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
- .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
- .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
- .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
- .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
- .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
-
- .vidioc_streamon = v4l2_m2m_ioctl_streamon,
- .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
-
- .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
- .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
-};
-
-static int tegra_init_ctrls(struct tegra_ctx *ctx)
-{
- unsigned int i;
- int err;
-
- err = v4l2_ctrl_handler_init(&ctx->hdl, ARRAY_SIZE(ctrl_cfgs));
- if (err)
- return err;
-
- for (i = 0; i < ARRAY_SIZE(ctrl_cfgs); i++) {
- ctx->ctrls[i] = v4l2_ctrl_new_custom(&ctx->hdl, &ctrl_cfgs[i],
- NULL);
- if (ctx->hdl.error) {
- err = ctx->hdl.error;
- goto free_ctrls;
- }
- }
-
- err = v4l2_ctrl_handler_setup(&ctx->hdl);
- if (err)
- goto free_ctrls;
-
- ctx->fh.ctrl_handler = &ctx->hdl;
-
- return 0;
-
-free_ctrls:
- v4l2_ctrl_handler_free(&ctx->hdl);
-
- return err;
-}
-
-static int tegra_init_m2m(struct tegra_ctx *ctx)
-{
- ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(ctx->vde->m2m,
- ctx, tegra_queue_init);
- if (IS_ERR(ctx->fh.m2m_ctx))
- return PTR_ERR(ctx->fh.m2m_ctx);
-
- return 0;
-}
-
-static int tegra_open(struct file *file)
-{
- struct tegra_vde *vde = video_drvdata(file);
- struct tegra_ctx *ctx;
- int err;
-
- ctx = kzalloc(offsetof(struct tegra_ctx, ctrls[ARRAY_SIZE(ctrl_cfgs)]),
- GFP_KERNEL);
- if (!ctx)
- return -ENOMEM;
-
- ctx->vde = vde;
- v4l2_fh_init(&ctx->fh, video_devdata(file));
- INIT_WORK(&ctx->work, tegra_decode_complete);
-
- err = tegra_init_ctrls(ctx);
- if (err) {
- v4l2_err(&vde->v4l2_dev, "failed to add controls: %d\n", err);
- goto free_ctx;
- }
-
- err = tegra_init_m2m(ctx);
- if (err) {
- v4l2_err(&vde->v4l2_dev, "failed to initialize m2m: %d\n", err);
- goto free_ctrls;
- }
-
- file->private_data = &ctx->fh;
- v4l2_fh_add(&ctx->fh);
-
- tegra_reset_coded_fmt(ctx);
- tegra_try_coded_fmt(file, file->private_data, &ctx->coded_fmt);
-
- tegra_reset_decoded_fmt(ctx);
- tegra_try_decoded_fmt(file, file->private_data, &ctx->decoded_fmt);
-
- return 0;
-
-free_ctrls:
- v4l2_ctrl_handler_free(&ctx->hdl);
-free_ctx:
- kfree(ctx);
-
- return err;
-}
-
-static int tegra_release(struct file *file)
-{
- struct v4l2_fh *fh = file->private_data;
- struct tegra_ctx *ctx = fh_to_tegra_ctx(fh);
- struct tegra_vde *vde = ctx->vde;
-
- v4l2_fh_del(fh);
- v4l2_m2m_ctx_release(fh->m2m_ctx);
- v4l2_ctrl_handler_free(&ctx->hdl);
- v4l2_fh_exit(fh);
- kfree(ctx);
-
- tegra_vde_dmabuf_cache_unmap_sync(vde);
-
- return 0;
-}
-
-static const struct v4l2_file_operations tegra_v4l2_fops = {
- .owner = THIS_MODULE,
- .open = tegra_open,
- .poll = v4l2_m2m_fop_poll,
- .mmap = v4l2_m2m_fop_mmap,
- .release = tegra_release,
- .unlocked_ioctl = video_ioctl2,
-};
-
-static void tegra_device_run(void *priv)
-{
- struct tegra_ctx *ctx = priv;
- struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
- struct media_request *src_req = src->vb2_buf.req_obj.req;
- int err;
-
- v4l2_ctrl_request_setup(src_req, &ctx->hdl);
-
- err = ctx->coded_fmt_desc->decode_run(ctx);
-
- v4l2_ctrl_request_complete(src_req, &ctx->hdl);
-
- if (err)
- tegra_job_finish(ctx, VB2_BUF_STATE_ERROR);
- else
- queue_work(ctx->vde->wq, &ctx->work);
-}
-
-static const struct v4l2_m2m_ops tegra_v4l2_m2m_ops = {
- .device_run = tegra_device_run,
-};
-
-static int tegra_request_validate(struct media_request *req)
-{
- unsigned int count;
-
- count = vb2_request_buffer_cnt(req);
- if (!count)
- return -ENOENT;
- else if (count > 1)
- return -EINVAL;
-
- return vb2_request_validate(req);
-}
-
-static const struct media_device_ops tegra_media_device_ops = {
- .req_validate = tegra_request_validate,
- .req_queue = v4l2_m2m_request_queue,
-};
-
-int tegra_vde_v4l2_init(struct tegra_vde *vde)
-{
- struct device *dev = vde->dev;
- int err;
-
- mutex_init(&vde->v4l2_lock);
- media_device_init(&vde->mdev);
- video_set_drvdata(&vde->vdev, vde);
-
- vde->vdev.lock = &vde->v4l2_lock,
- vde->vdev.fops = &tegra_v4l2_fops,
- vde->vdev.vfl_dir = VFL_DIR_M2M,
- vde->vdev.release = video_device_release_empty,
- vde->vdev.v4l2_dev = &vde->v4l2_dev;
- vde->vdev.ioctl_ops = &tegra_v4l2_ioctl_ops,
- vde->vdev.device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING,
-
- vde->v4l2_dev.mdev = &vde->mdev;
- vde->mdev.ops = &tegra_media_device_ops;
- vde->mdev.dev = dev;
-
- strscpy(vde->mdev.model, "tegra-vde", sizeof(vde->mdev.model));
- strscpy(vde->vdev.name, "tegra-vde", sizeof(vde->vdev.name));
- strscpy(vde->mdev.bus_info, "platform:tegra-vde",
- sizeof(vde->mdev.bus_info));
-
- vde->wq = create_workqueue("tegra-vde");
- if (!vde->wq)
- return -ENOMEM;
-
- err = media_device_register(&vde->mdev);
- if (err) {
- dev_err(dev, "failed to register media device: %d\n", err);
- goto clean_up_media_device;
- }
-
- err = v4l2_device_register(dev, &vde->v4l2_dev);
- if (err) {
- dev_err(dev, "failed to register v4l2 device: %d\n", err);
- goto unreg_media_device;
- }
-
- err = video_register_device(&vde->vdev, VFL_TYPE_VIDEO, -1);
- if (err) {
- dev_err(dev, "failed to register video device: %d\n", err);
- goto unreg_v4l2;
- }
-
- vde->m2m = v4l2_m2m_init(&tegra_v4l2_m2m_ops);
- err = PTR_ERR_OR_ZERO(vde->m2m);
- if (err) {
- dev_err(dev, "failed to initialize m2m device: %d\n", err);
- goto unreg_video_device;
- }
-
- err = v4l2_m2m_register_media_controller(vde->m2m, &vde->vdev,
- MEDIA_ENT_F_PROC_VIDEO_DECODER);
- if (err) {
- dev_err(dev, "failed to register media controller: %d\n", err);
- goto release_m2m;
- }
-
- v4l2_info(&vde->v4l2_dev, "v4l2 device registered as /dev/video%d\n",
- vde->vdev.num);
-
- return 0;
-
-release_m2m:
- v4l2_m2m_release(vde->m2m);
-unreg_video_device:
- video_unregister_device(&vde->vdev);
-unreg_v4l2:
- v4l2_device_unregister(&vde->v4l2_dev);
-unreg_media_device:
- media_device_unregister(&vde->mdev);
-clean_up_media_device:
- media_device_cleanup(&vde->mdev);
-
- destroy_workqueue(vde->wq);
-
- return err;
-}
-
-void tegra_vde_v4l2_deinit(struct tegra_vde *vde)
-{
- v4l2_m2m_unregister_media_controller(vde->m2m);
- v4l2_m2m_release(vde->m2m);
-
- video_unregister_device(&vde->vdev);
- v4l2_device_unregister(&vde->v4l2_dev);
-
- media_device_unregister(&vde->mdev);
- media_device_cleanup(&vde->mdev);
-
- destroy_workqueue(vde->wq);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * NVIDIA Tegra Video decoder driver
- *
- * Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com>
- *
- */
-
-#include <linux/clk.h>
-#include <linux/dma-buf.h>
-#include <linux/genalloc.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/of_device.h>
-#include <linux/pm_runtime.h>
-#include <linux/reset.h>
-#include <linux/slab.h>
-#include <linux/uaccess.h>
-
-#include <soc/tegra/common.h>
-#include <soc/tegra/pmc.h>
-
-#include "vde.h"
-
-#define CREATE_TRACE_POINTS
-#include "trace.h"
-
-void tegra_vde_writel(struct tegra_vde *vde, u32 value,
- void __iomem *base, u32 offset)
-{
- trace_vde_writel(vde, base, offset, value);
-
- writel_relaxed(value, base + offset);
-}
-
-u32 tegra_vde_readl(struct tegra_vde *vde, void __iomem *base, u32 offset)
-{
- u32 value = readl_relaxed(base + offset);
-
- trace_vde_readl(vde, base, offset, value);
-
- return value;
-}
-
-void tegra_vde_set_bits(struct tegra_vde *vde, u32 mask,
- void __iomem *base, u32 offset)
-{
- u32 value = tegra_vde_readl(vde, base, offset);
-
- tegra_vde_writel(vde, value | mask, base, offset);
-}
-
-int tegra_vde_alloc_bo(struct tegra_vde *vde,
- struct tegra_vde_bo **ret_bo,
- enum dma_data_direction dma_dir,
- size_t size)
-{
- struct device *dev = vde->dev;
- struct tegra_vde_bo *bo;
- int err;
-
- bo = kzalloc(sizeof(*bo), GFP_KERNEL);
- if (!bo)
- return -ENOMEM;
-
- bo->vde = vde;
- bo->size = size;
- bo->dma_dir = dma_dir;
- bo->dma_attrs = DMA_ATTR_WRITE_COMBINE |
- DMA_ATTR_NO_KERNEL_MAPPING;
-
- if (!vde->domain)
- bo->dma_attrs |= DMA_ATTR_FORCE_CONTIGUOUS;
-
- bo->dma_cookie = dma_alloc_attrs(dev, bo->size, &bo->dma_handle,
- GFP_KERNEL, bo->dma_attrs);
- if (!bo->dma_cookie) {
- dev_err(dev, "Failed to allocate DMA buffer of size: %zu\n",
- bo->size);
- err = -ENOMEM;
- goto free_bo;
- }
-
- err = dma_get_sgtable_attrs(dev, &bo->sgt, bo->dma_cookie,
- bo->dma_handle, bo->size, bo->dma_attrs);
- if (err) {
- dev_err(dev, "Failed to get DMA buffer SG table: %d\n", err);
- goto free_attrs;
- }
-
- err = dma_map_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs);
- if (err) {
- dev_err(dev, "Failed to map DMA buffer SG table: %d\n", err);
- goto free_table;
- }
-
- if (vde->domain) {
- err = tegra_vde_iommu_map(vde, &bo->sgt, &bo->iova, bo->size);
- if (err) {
- dev_err(dev, "Failed to map DMA buffer IOVA: %d\n", err);
- goto unmap_sgtable;
- }
-
- bo->dma_addr = iova_dma_addr(&vde->iova, bo->iova);
- } else {
- bo->dma_addr = sg_dma_address(bo->sgt.sgl);
- }
-
- *ret_bo = bo;
-
- return 0;
-
-unmap_sgtable:
- dma_unmap_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs);
-free_table:
- sg_free_table(&bo->sgt);
-free_attrs:
- dma_free_attrs(dev, bo->size, bo->dma_cookie, bo->dma_handle,
- bo->dma_attrs);
-free_bo:
- kfree(bo);
-
- return err;
-}
-
-void tegra_vde_free_bo(struct tegra_vde_bo *bo)
-{
- struct tegra_vde *vde = bo->vde;
- struct device *dev = vde->dev;
-
- if (vde->domain)
- tegra_vde_iommu_unmap(vde, bo->iova);
-
- dma_unmap_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs);
-
- sg_free_table(&bo->sgt);
-
- dma_free_attrs(dev, bo->size, bo->dma_cookie, bo->dma_handle,
- bo->dma_attrs);
- kfree(bo);
-}
-
-static irqreturn_t tegra_vde_isr(int irq, void *data)
-{
- struct tegra_vde *vde = data;
-
- if (completion_done(&vde->decode_completion))
- return IRQ_NONE;
-
- tegra_vde_set_bits(vde, 0, vde->frameid, 0x208);
- complete(&vde->decode_completion);
-
- return IRQ_HANDLED;
-}
-
-static __maybe_unused int tegra_vde_runtime_suspend(struct device *dev)
-{
- struct tegra_vde *vde = dev_get_drvdata(dev);
- int err;
-
- if (!dev->pm_domain) {
- err = tegra_powergate_power_off(TEGRA_POWERGATE_VDEC);
- if (err) {
- dev_err(dev, "Failed to power down HW: %d\n", err);
- return err;
- }
- }
-
- clk_disable_unprepare(vde->clk);
- reset_control_release(vde->rst);
- reset_control_release(vde->rst_mc);
-
- return 0;
-}
-
-static __maybe_unused int tegra_vde_runtime_resume(struct device *dev)
-{
- struct tegra_vde *vde = dev_get_drvdata(dev);
- int err;
-
- err = reset_control_acquire(vde->rst_mc);
- if (err) {
- dev_err(dev, "Failed to acquire mc reset: %d\n", err);
- return err;
- }
-
- err = reset_control_acquire(vde->rst);
- if (err) {
- dev_err(dev, "Failed to acquire reset: %d\n", err);
- goto release_mc_reset;
- }
-
- if (!dev->pm_domain) {
- err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_VDEC,
- vde->clk, vde->rst);
- if (err) {
- dev_err(dev, "Failed to power up HW : %d\n", err);
- goto release_reset;
- }
- } else {
- /*
- * tegra_powergate_sequence_power_up() leaves clocks enabled,
- * while GENPD not.
- */
- err = clk_prepare_enable(vde->clk);
- if (err) {
- dev_err(dev, "Failed to enable clock: %d\n", err);
- goto release_reset;
- }
- }
-
- return 0;
-
-release_reset:
- reset_control_release(vde->rst);
-release_mc_reset:
- reset_control_release(vde->rst_mc);
-
- return err;
-}
-
-static int tegra_vde_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct tegra_vde *vde;
- int irq, err;
-
- vde = devm_kzalloc(dev, sizeof(*vde), GFP_KERNEL);
- if (!vde)
- return -ENOMEM;
-
- platform_set_drvdata(pdev, vde);
-
- vde->soc = of_device_get_match_data(&pdev->dev);
- vde->dev = dev;
-
- vde->sxe = devm_platform_ioremap_resource_byname(pdev, "sxe");
- if (IS_ERR(vde->sxe))
- return PTR_ERR(vde->sxe);
-
- vde->bsev = devm_platform_ioremap_resource_byname(pdev, "bsev");
- if (IS_ERR(vde->bsev))
- return PTR_ERR(vde->bsev);
-
- vde->mbe = devm_platform_ioremap_resource_byname(pdev, "mbe");
- if (IS_ERR(vde->mbe))
- return PTR_ERR(vde->mbe);
-
- vde->ppe = devm_platform_ioremap_resource_byname(pdev, "ppe");
- if (IS_ERR(vde->ppe))
- return PTR_ERR(vde->ppe);
-
- vde->mce = devm_platform_ioremap_resource_byname(pdev, "mce");
- if (IS_ERR(vde->mce))
- return PTR_ERR(vde->mce);
-
- vde->tfe = devm_platform_ioremap_resource_byname(pdev, "tfe");
- if (IS_ERR(vde->tfe))
- return PTR_ERR(vde->tfe);
-
- vde->ppb = devm_platform_ioremap_resource_byname(pdev, "ppb");
- if (IS_ERR(vde->ppb))
- return PTR_ERR(vde->ppb);
-
- vde->vdma = devm_platform_ioremap_resource_byname(pdev, "vdma");
- if (IS_ERR(vde->vdma))
- return PTR_ERR(vde->vdma);
-
- vde->frameid = devm_platform_ioremap_resource_byname(pdev, "frameid");
- if (IS_ERR(vde->frameid))
- return PTR_ERR(vde->frameid);
-
- vde->clk = devm_clk_get(dev, NULL);
- if (IS_ERR(vde->clk)) {
- err = PTR_ERR(vde->clk);
- dev_err(dev, "Could not get VDE clk %d\n", err);
- return err;
- }
-
- vde->rst = devm_reset_control_get_exclusive_released(dev, NULL);
- if (IS_ERR(vde->rst)) {
- err = PTR_ERR(vde->rst);
- dev_err(dev, "Could not get VDE reset %d\n", err);
- return err;
- }
-
- vde->rst_mc = devm_reset_control_get_optional_exclusive_released(dev, "mc");
- if (IS_ERR(vde->rst_mc)) {
- err = PTR_ERR(vde->rst_mc);
- dev_err(dev, "Could not get MC reset %d\n", err);
- return err;
- }
-
- irq = platform_get_irq_byname(pdev, "sync-token");
- if (irq < 0)
- return irq;
-
- err = devm_request_irq(dev, irq, tegra_vde_isr, 0,
- dev_name(dev), vde);
- if (err) {
- dev_err(dev, "Could not request IRQ %d\n", err);
- return err;
- }
-
- err = devm_tegra_core_dev_init_opp_table_common(dev);
- if (err) {
- dev_err(dev, "Could initialize OPP table %d\n", err);
- return err;
- }
-
- vde->iram_pool = of_gen_pool_get(dev->of_node, "iram", 0);
- if (!vde->iram_pool) {
- dev_err(dev, "Could not get IRAM pool\n");
- return -EPROBE_DEFER;
- }
-
- vde->iram = gen_pool_dma_alloc(vde->iram_pool,
- gen_pool_size(vde->iram_pool),
- &vde->iram_lists_addr);
- if (!vde->iram) {
- dev_err(dev, "Could not reserve IRAM\n");
- return -ENOMEM;
- }
-
- INIT_LIST_HEAD(&vde->map_list);
- mutex_init(&vde->map_lock);
- mutex_init(&vde->lock);
- init_completion(&vde->decode_completion);
-
- err = tegra_vde_iommu_init(vde);
- if (err) {
- dev_err(dev, "Failed to initialize IOMMU: %d\n", err);
- goto err_gen_free;
- }
-
- pm_runtime_enable(dev);
- pm_runtime_use_autosuspend(dev);
- pm_runtime_set_autosuspend_delay(dev, 300);
-
- /*
- * VDE partition may be left ON after bootloader, hence let's
- * power-cycle it in order to put hardware into a predictable lower
- * power state.
- */
- err = pm_runtime_resume_and_get(dev);
- if (err)
- goto err_pm_runtime;
-
- pm_runtime_put(dev);
-
- err = tegra_vde_alloc_bo(vde, &vde->secure_bo, DMA_FROM_DEVICE, 4096);
- if (err) {
- dev_err(dev, "Failed to allocate secure BO: %d\n", err);
- goto err_pm_runtime;
- }
-
- err = tegra_vde_v4l2_init(vde);
- if (err) {
- dev_err(dev, "Failed to initialize V4L2: %d\n", err);
- goto err_free_secure_bo;
- }
-
- return 0;
-
-err_free_secure_bo:
- tegra_vde_free_bo(vde->secure_bo);
-err_pm_runtime:
- pm_runtime_dont_use_autosuspend(dev);
- pm_runtime_disable(dev);
-
- tegra_vde_iommu_deinit(vde);
-
-err_gen_free:
- gen_pool_free(vde->iram_pool, (unsigned long)vde->iram,
- gen_pool_size(vde->iram_pool));
-
- return err;
-}
-
-static int tegra_vde_remove(struct platform_device *pdev)
-{
- struct tegra_vde *vde = platform_get_drvdata(pdev);
- struct device *dev = &pdev->dev;
-
- tegra_vde_v4l2_deinit(vde);
- tegra_vde_free_bo(vde->secure_bo);
-
- /*
- * As it increments RPM usage_count even on errors, we don't need to
- * check the returned code here.
- */
- pm_runtime_get_sync(dev);
-
- pm_runtime_dont_use_autosuspend(dev);
- pm_runtime_disable(dev);
-
- /*
- * Balance RPM state, the VDE power domain is left ON and hardware
- * is clock-gated. It's safe to reboot machine now.
- */
- pm_runtime_put_noidle(dev);
- clk_disable_unprepare(vde->clk);
-
- tegra_vde_dmabuf_cache_unmap_all(vde);
- tegra_vde_iommu_deinit(vde);
-
- gen_pool_free(vde->iram_pool, (unsigned long)vde->iram,
- gen_pool_size(vde->iram_pool));
-
- return 0;
-}
-
-static void tegra_vde_shutdown(struct platform_device *pdev)
-{
- /*
- * On some devices bootloader isn't ready to a power-gated VDE on
- * a warm-reboot, machine will hang in that case.
- */
- pm_runtime_get_sync(&pdev->dev);
-}
-
-static __maybe_unused int tegra_vde_pm_suspend(struct device *dev)
-{
- struct tegra_vde *vde = dev_get_drvdata(dev);
- int err;
-
- mutex_lock(&vde->lock);
-
- err = pm_runtime_force_suspend(dev);
- if (err < 0)
- return err;
-
- return 0;
-}
-
-static __maybe_unused int tegra_vde_pm_resume(struct device *dev)
-{
- struct tegra_vde *vde = dev_get_drvdata(dev);
- int err;
-
- err = pm_runtime_force_resume(dev);
- if (err < 0)
- return err;
-
- mutex_unlock(&vde->lock);
-
- return 0;
-}
-
-static const struct dev_pm_ops tegra_vde_pm_ops = {
- SET_RUNTIME_PM_OPS(tegra_vde_runtime_suspend,
- tegra_vde_runtime_resume,
- NULL)
- SET_SYSTEM_SLEEP_PM_OPS(tegra_vde_pm_suspend,
- tegra_vde_pm_resume)
-};
-
-static const u32 tegra124_decoded_fmts[] = {
- /* TBD: T124 supports only a non-standard Tegra tiled format */
-};
-
-static const struct tegra_coded_fmt_desc tegra124_coded_fmts[] = {
- {
- .fourcc = V4L2_PIX_FMT_H264_SLICE,
- .frmsize = {
- .min_width = 16,
- .max_width = 1920,
- .step_width = 16,
- .min_height = 16,
- .max_height = 2032,
- .step_height = 16,
- },
- .num_decoded_fmts = ARRAY_SIZE(tegra124_decoded_fmts),
- .decoded_fmts = tegra124_decoded_fmts,
- .decode_run = tegra_vde_h264_decode_run,
- .decode_wait = tegra_vde_h264_decode_wait,
- },
-};
-
-static const u32 tegra20_decoded_fmts[] = {
- V4L2_PIX_FMT_YUV420M,
- V4L2_PIX_FMT_YVU420M,
-};
-
-static const struct tegra_coded_fmt_desc tegra20_coded_fmts[] = {
- {
- .fourcc = V4L2_PIX_FMT_H264_SLICE,
- .frmsize = {
- .min_width = 16,
- .max_width = 1920,
- .step_width = 16,
- .min_height = 16,
- .max_height = 2032,
- .step_height = 16,
- },
- .num_decoded_fmts = ARRAY_SIZE(tegra20_decoded_fmts),
- .decoded_fmts = tegra20_decoded_fmts,
- .decode_run = tegra_vde_h264_decode_run,
- .decode_wait = tegra_vde_h264_decode_wait,
- },
-};
-
-static const struct tegra_vde_soc tegra124_vde_soc = {
- .supports_ref_pic_marking = true,
- .coded_fmts = tegra124_coded_fmts,
- .num_coded_fmts = ARRAY_SIZE(tegra124_coded_fmts),
-};
-
-static const struct tegra_vde_soc tegra114_vde_soc = {
- .supports_ref_pic_marking = true,
- .coded_fmts = tegra20_coded_fmts,
- .num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts),
-};
-
-static const struct tegra_vde_soc tegra30_vde_soc = {
- .supports_ref_pic_marking = false,
- .coded_fmts = tegra20_coded_fmts,
- .num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts),
-};
-
-static const struct tegra_vde_soc tegra20_vde_soc = {
- .supports_ref_pic_marking = false,
- .coded_fmts = tegra20_coded_fmts,
- .num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts),
-};
-
-static const struct of_device_id tegra_vde_of_match[] = {
- { .compatible = "nvidia,tegra124-vde", .data = &tegra124_vde_soc },
- { .compatible = "nvidia,tegra114-vde", .data = &tegra114_vde_soc },
- { .compatible = "nvidia,tegra30-vde", .data = &tegra30_vde_soc },
- { .compatible = "nvidia,tegra20-vde", .data = &tegra20_vde_soc },
- { },
-};
-MODULE_DEVICE_TABLE(of, tegra_vde_of_match);
-
-static struct platform_driver tegra_vde_driver = {
- .probe = tegra_vde_probe,
- .remove = tegra_vde_remove,
- .shutdown = tegra_vde_shutdown,
- .driver = {
- .name = "tegra-vde",
- .of_match_table = tegra_vde_of_match,
- .pm = &tegra_vde_pm_ops,
- },
-};
-module_platform_driver(tegra_vde_driver);
-
-MODULE_DESCRIPTION("NVIDIA Tegra Video Decoder driver");
-MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * NVIDIA Tegra Video decoder driver
- *
- * Copyright (C) 2016-2019 GRATE-DRIVER project
- */
-
-#ifndef TEGRA_VDE_H
-#define TEGRA_VDE_H
-
-#include <linux/completion.h>
-#include <linux/dma-direction.h>
-#include <linux/iova.h>
-#include <linux/list.h>
-#include <linux/mutex.h>
-#include <linux/types.h>
-#include <linux/workqueue.h>
-
-#include <media/media-device.h>
-#include <media/videobuf2-dma-contig.h>
-#include <media/videobuf2-dma-sg.h>
-#include <media/v4l2-ctrls.h>
-#include <media/v4l2-device.h>
-#include <media/v4l2-event.h>
-#include <media/v4l2-ioctl.h>
-#include <media/v4l2-mem2mem.h>
-
-#define ICMDQUE_WR 0x00
-#define CMDQUE_CONTROL 0x08
-#define INTR_STATUS 0x18
-#define BSE_INT_ENB 0x40
-#define BSE_CONFIG 0x44
-
-#define BSE_ICMDQUE_EMPTY BIT(3)
-#define BSE_DMA_BUSY BIT(23)
-
-#define BSEV_ALIGN SZ_1
-#define FRAMEID_ALIGN SZ_256
-#define SXE_BUFFER SZ_32K
-#define VDE_ATOM SZ_16
-
-struct clk;
-struct dma_buf;
-struct gen_pool;
-struct tegra_ctx;
-struct iommu_group;
-struct iommu_domain;
-struct reset_control;
-struct dma_buf_attachment;
-struct tegra_vde_h264_frame;
-struct tegra_vde_h264_decoder_ctx;
-
-struct tegra_video_frame {
- struct dma_buf_attachment *y_dmabuf_attachment;
- struct dma_buf_attachment *cb_dmabuf_attachment;
- struct dma_buf_attachment *cr_dmabuf_attachment;
- struct dma_buf_attachment *aux_dmabuf_attachment;
- dma_addr_t y_addr;
- dma_addr_t cb_addr;
- dma_addr_t cr_addr;
- dma_addr_t aux_addr;
- u32 frame_num;
- u32 flags;
- u32 luma_atoms_pitch;
- u32 chroma_atoms_pitch;
-};
-
-struct tegra_coded_fmt_desc {
- u32 fourcc;
- struct v4l2_frmsize_stepwise frmsize;
- unsigned int num_decoded_fmts;
- const u32 *decoded_fmts;
- int (*decode_run)(struct tegra_ctx *ctx);
- int (*decode_wait)(struct tegra_ctx *ctx);
-};
-
-struct tegra_vde_soc {
- bool supports_ref_pic_marking;
- const struct tegra_coded_fmt_desc *coded_fmts;
- u32 num_coded_fmts;
-};
-
-struct tegra_vde_bo {
- struct iova *iova;
- struct sg_table sgt;
- struct tegra_vde *vde;
- enum dma_data_direction dma_dir;
- unsigned long dma_attrs;
- dma_addr_t dma_handle;
- dma_addr_t dma_addr;
- void *dma_cookie;
- size_t size;
-};
-
-struct tegra_vde {
- void __iomem *sxe;
- void __iomem *bsev;
- void __iomem *mbe;
- void __iomem *ppe;
- void __iomem *mce;
- void __iomem *tfe;
- void __iomem *ppb;
- void __iomem *vdma;
- void __iomem *frameid;
- struct device *dev;
- struct mutex lock;
- struct mutex map_lock;
- struct list_head map_list;
- struct reset_control *rst;
- struct reset_control *rst_mc;
- struct gen_pool *iram_pool;
- struct completion decode_completion;
- struct clk *clk;
- struct iommu_domain *domain;
- struct iommu_group *group;
- struct iova_domain iova;
- struct iova *iova_resv_static_addresses;
- struct iova *iova_resv_last_page;
- const struct tegra_vde_soc *soc;
- struct tegra_vde_bo *secure_bo;
- dma_addr_t bitstream_data_addr;
- dma_addr_t iram_lists_addr;
- u32 *iram;
- struct v4l2_device v4l2_dev;
- struct v4l2_m2m_dev *m2m;
- struct media_device mdev;
- struct video_device vdev;
- struct mutex v4l2_lock;
- struct workqueue_struct *wq;
- struct tegra_video_frame frames[V4L2_H264_NUM_DPB_ENTRIES + 1];
-};
-
-int tegra_vde_alloc_bo(struct tegra_vde *vde,
- struct tegra_vde_bo **ret_bo,
- enum dma_data_direction dma_dir,
- size_t size);
-void tegra_vde_free_bo(struct tegra_vde_bo *bo);
-
-struct tegra_ctx_h264 {
- const struct v4l2_ctrl_h264_decode_params *decode_params;
- const struct v4l2_ctrl_h264_sps *sps;
- const struct v4l2_ctrl_h264_pps *pps;
-};
-
-struct tegra_ctx {
- struct tegra_vde *vde;
- struct tegra_ctx_h264 h264;
- struct work_struct work;
- struct v4l2_fh fh;
- struct v4l2_ctrl_handler hdl;
- struct v4l2_format coded_fmt;
- struct v4l2_format decoded_fmt;
- const struct tegra_coded_fmt_desc *coded_fmt_desc;
- struct v4l2_ctrl *ctrls[];
-};
-
-struct tegra_m2m_buffer {
- struct v4l2_m2m_buffer m2m;
- struct dma_buf_attachment *a[VB2_MAX_PLANES];
- dma_addr_t dma_base[VB2_MAX_PLANES];
- dma_addr_t dma_addr[VB2_MAX_PLANES];
- struct iova *iova[VB2_MAX_PLANES];
- struct tegra_vde_bo *aux;
- bool b_frame;
-};
-
-static inline struct tegra_m2m_buffer *
-vb_to_tegra_buf(struct vb2_buffer *vb)
-{
- struct v4l2_m2m_buffer *m2m = container_of(vb, struct v4l2_m2m_buffer,
- vb.vb2_buf);
-
- return container_of(m2m, struct tegra_m2m_buffer, m2m);
-}
-
-void tegra_vde_prepare_control_data(struct tegra_ctx *ctx, u32 id);
-
-void tegra_vde_writel(struct tegra_vde *vde, u32 value, void __iomem *base,
- u32 offset);
-u32 tegra_vde_readl(struct tegra_vde *vde, void __iomem *base, u32 offset);
-void tegra_vde_set_bits(struct tegra_vde *vde, u32 mask, void __iomem *base,
- u32 offset);
-
-int tegra_vde_h264_decode_run(struct tegra_ctx *ctx);
-int tegra_vde_h264_decode_wait(struct tegra_ctx *ctx);
-
-int tegra_vde_iommu_init(struct tegra_vde *vde);
-void tegra_vde_iommu_deinit(struct tegra_vde *vde);
-int tegra_vde_iommu_map(struct tegra_vde *vde,
- struct sg_table *sgt,
- struct iova **iovap,
- size_t size);
-void tegra_vde_iommu_unmap(struct tegra_vde *vde, struct iova *iova);
-
-int tegra_vde_dmabuf_cache_map(struct tegra_vde *vde,
- struct dma_buf *dmabuf,
- enum dma_data_direction dma_dir,
- struct dma_buf_attachment **ap,
- dma_addr_t *addrp);
-void tegra_vde_dmabuf_cache_unmap(struct tegra_vde *vde,
- struct dma_buf_attachment *a,
- bool release);
-void tegra_vde_dmabuf_cache_unmap_sync(struct tegra_vde *vde);
-void tegra_vde_dmabuf_cache_unmap_all(struct tegra_vde *vde);
-
-static __maybe_unused char const *
-tegra_vde_reg_base_name(struct tegra_vde *vde, void __iomem *base)
-{
- if (vde->sxe == base)
- return "SXE";
-
- if (vde->bsev == base)
- return "BSEV";
-
- if (vde->mbe == base)
- return "MBE";
-
- if (vde->ppe == base)
- return "PPE";
-
- if (vde->mce == base)
- return "MCE";
-
- if (vde->tfe == base)
- return "TFE";
-
- if (vde->ppb == base)
- return "PPB";
-
- if (vde->vdma == base)
- return "VDMA";
-
- if (vde->frameid == base)
- return "FRAMEID";
-
- return "???";
-}
-
-int tegra_vde_v4l2_init(struct tegra_vde *vde);
-void tegra_vde_v4l2_deinit(struct tegra_vde *vde);
-
-#endif /* TEGRA_VDE_H */
projects / linux-2.6-microblaze.git / commitdiff