ARM64: dts: meson: fix clock source of the pclk for UART_AO
authorYixun Lan <yixun.lan@amlogic.com>
Wed, 28 Mar 2018 03:01:30 +0000 (11:01 +0800)
committerKevin Hilman <khilman@baylibre.com>
Wed, 23 May 2018 18:31:54 +0000 (11:31 -0700)
>From the hardware perspective, the actual pclk of the AO uarts
is the corresponding clkc_ao uart gate, not the main clock controller clk81.
This was not problem so far, because the uart_gate had
the CLK_IGNORE_UNUSED flag, which kept the gate open.

We plan to remove the CLK_IGNORE_UNUSED flag in another patch,
but before doing that, we need to fix the clock in the DTS file.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

index ff3749e..fee8773 100644 (file)
                                compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
                                reg = <0x0 0x3000 0x0 0x18>;
                                interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
-                               clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+                               clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
                                clock-names = "xtal", "pclk", "baud";
                                status = "disabled";
                        };
                                compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
                                reg = <0x0 0x4000 0x0 0x18>;
                                interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
-                               clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+                               clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
                                clock-names = "xtal", "pclk", "baud";
                                status = "disabled";
                        };
index 1cbb082..98cbba6 100644 (file)
 };
 
 &uart_AO {
-       clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+       clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
        clock-names = "xtal", "pclk", "baud";
 };
 
 &uart_AO_B {
-       clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+       clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
        clock-names = "xtal", "pclk", "baud";
 };
 
index 6e4a071..27538ee 100644 (file)
 };
 
 &uart_AO {
-       clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+       clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
        clock-names = "xtal", "pclk", "baud";
 };
 
 &uart_AO_B {
-       clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+       clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
        clock-names = "xtal", "pclk", "baud";
 };