drm/msm/dpu: Tear down DSC datapath on encoder cleanup

Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(),
dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions
to tear down DSC data path if DSC data path was setup previous.

Changes in V10:
-- pass ctl directly instead of dpu_enc to dsc_pipe_cfg()
-- move both dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() to above phys_cleanup()

Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/539515/
Link: https://lore.kernel.org/r/1685036458-22683-11-git-send-email-quic_khsieh@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 95b2bd9..2c9af33 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2036,6 +2036,41 @@ static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
        }
 }
 
+static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl,
+                                    struct dpu_hw_dsc *hw_dsc,
+                                    struct dpu_hw_pingpong *hw_pp)
+{
+       if (hw_dsc->ops.dsc_disable)
+               hw_dsc->ops.dsc_disable(hw_dsc);
+
+       if (hw_pp->ops.disable_dsc)
+               hw_pp->ops.disable_dsc(hw_pp);
+
+       if (hw_dsc->ops.dsc_bind_pingpong_blk)
+               hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE);
+
+       if (ctl->ops.update_pending_flush_dsc)
+               ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
+}
+
+static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc)
+{
+       /* coding only for 2LM, 2enc, 1 dsc config */
+       struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
+       struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
+       struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
+       struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
+       int i;
+
+       for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
+               hw_pp[i] = dpu_enc->hw_pp[i];
+               hw_dsc[i] = dpu_enc->hw_dsc[i];
+
+               if (hw_pp[i] && hw_dsc[i])
+                       dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]);
+       }
+}
+
 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
 {
        struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
@@ -2086,8 +2121,12 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
                                        phys_enc->hw_pp->merge_3d->idx);
        }
 
+       if (dpu_enc->dsc)
+               dpu_encoder_unprep_dsc(dpu_enc);
+
        intf_cfg.stream_sel = 0; /* Don't care value for video mode */
        intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+       intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
 
        if (phys_enc->hw_intf)
                intf_cfg.intf = phys_enc->hw_intf->idx;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 0007d14..c278fb9 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -576,6 +576,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx,
        u32 intf_active = 0;
        u32 wb_active = 0;
        u32 merge3d_active = 0;
+       u32 dsc_active;
 
        /*
         * This API resets each portion of the CTL path namely,
@@ -605,6 +606,12 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx,
                wb_active &= ~BIT(cfg->wb - WB_0);
                DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
        }
+
+       if (cfg->dsc) {
+               dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE);
+               dsc_active &= ~cfg->dsc;
+               DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
+       }
 }
 
 static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx,