spi: atmel-quadspi: cache MR value to avoid a write access

Set the controller by default in Serial Memory Mode (SMM) at probe.
Cache Mode Register (MR) value to avoid write access when setting
the controller in serial memory mode at exec_op().

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index ddc7124..d6864d2 100644 (file)
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -155,6 +155,7 @@ struct atmel_qspi {
        struct clk              *clk;
        struct platform_device  *pdev;
        u32                     pending;
+       u32                     mr;
        struct completion       cmd_completion;
 };
 
@@ -238,7 +239,14 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
        icr = QSPI_ICR_INST(op->cmd.opcode);
        ifr = QSPI_IFR_INSTEN;
 
-       qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
+       /*
+        * If the QSPI controller is set in regular SPI mode, set it in
+        * Serial Memory Mode (SMM).
+        */
+       if (aq->mr != QSPI_MR_SMM) {
+               qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
+               aq->mr = QSPI_MR_SMM;
+       }
 
        mode = find_mode(op);
        if (mode < 0)
@@ -381,6 +389,10 @@ static int atmel_qspi_init(struct atmel_qspi *aq)
        /* Reset the QSPI controller */
        qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
 
+       /* Set the QSPI controller by default in Serial Memory Mode */
+       qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
+       aq->mr = QSPI_MR_SMM;
+
        /* Enable the QSPI controller */
        qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);