ARM: dts: at91: use generic name for reset controller
authorClaudiu Beznea <claudiu.beznea@microchip.com>
Fri, 10 Jun 2022 09:24:06 +0000 (12:24 +0300)
committerClaudiu Beznea <claudiu.beznea@microchip.com>
Mon, 4 Jul 2022 05:34:03 +0000 (08:34 +0300)
Use generic name for reset controller of AT91 devices to comply with
DT specifications.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220610092414.1816571-2-claudiu.beznea@microchip.com
arch/arm/boot/dts/at91sam9260.dtsi
arch/arm/boot/dts/at91sam9261.dtsi
arch/arm/boot/dts/at91sam9263.dtsi
arch/arm/boot/dts/at91sam9g45.dtsi
arch/arm/boot/dts/at91sam9n12.dtsi
arch/arm/boot/dts/at91sam9rl.dtsi
arch/arm/boot/dts/at91sam9x5.dtsi
arch/arm/boot/dts/sam9x60.dtsi
arch/arm/boot/dts/sama5d2.dtsi
arch/arm/boot/dts/sama5d3.dtsi
arch/arm/boot/dts/sama5d4.dtsi

index 7368347..9d9820d 100644 (file)
                                clock-names = "slow_xtal", "main_xtal";
                        };
 
-                       rstc@fffffd00 {
+                       reset-controller@fffffd00 {
                                compatible = "atmel,at91sam9260-rstc";
                                reg = <0xfffffd00 0x10>;
                                clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
index 7adc36c..259aca5 100644 (file)
                                clock-names = "slow_xtal", "main_xtal";
                        };
 
-                       rstc@fffffd00 {
+                       reset-controller@fffffd00 {
                                compatible = "atmel,at91sam9260-rstc";
                                reg = <0xfffffd00 0x10>;
                                clocks = <&slow_xtal>;
index fe45d96..c080df8 100644 (file)
                                clock-names = "t0_clk", "slow_clk";
                        };
 
-                       rstc@fffffd00 {
+                       reset-controller@fffffd00 {
                                compatible = "atmel,at91sam9260-rstc";
                                reg = <0xfffffd00 0x10>;
                                clocks = <&slow_xtal>;
index 2ab730f..0979456 100644 (file)
                                clock-names = "slow_clk", "main_xtal";
                        };
 
-                       rstc@fffffd00 {
+                       reset-controller@fffffd00 {
                                compatible = "atmel,at91sam9g45-rstc";
                                reg = <0xfffffd00 0x10>;
                                clocks = <&clk32k>;
index 0785389..556f35c 100644 (file)
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                        };
 
-                       rstc@fffffe00 {
+                       reset-controller@fffffe00 {
                                compatible = "atmel,at91sam9g45-rstc";
                                reg = <0xfffffe00 0x10>;
                                clocks = <&clk32k>;
index 730d118..12c6348 100644 (file)
                                clock-names = "slow_clk", "main_xtal";
                        };
 
-                       rstc@fffffd00 {
+                       reset-controller@fffffd00 {
                                compatible = "atmel,at91sam9260-rstc";
                                reg = <0xfffffd00 0x10>;
                                clocks = <&clk32k>;
index 395e883..ea3b113 100644 (file)
                                clock-names = "slow_clk", "main_xtal";
                        };
 
-                       reset_controller: rstc@fffffe00 {
+                       reset_controller: reset-controller@fffffe00 {
                                compatible = "atmel,at91sam9g45-rstc";
                                reg = <0xfffffe00 0x10>;
                                clocks = <&clk32k>;
index c328b67..6b1d449 100644 (file)
                                clock-names = "td_slck", "md_slck", "main_xtal";
                        };
 
-                       reset_controller: rstc@fffffe00 {
+                       reset_controller: reset-controller@fffffe00 {
                                compatible = "microchip,sam9x60-rstc";
                                reg = <0xfffffe00 0x10>;
                                clocks = <&clk32k 0>;
index 5b2f2e9..0baa186 100644 (file)
                                ranges = <0 0xf8044000 0x1420>;
                        };
 
-                       reset_controller: rstc@f8048000 {
+                       reset_controller: reset-controller@f8048000 {
                                compatible = "atmel,sama5d3-rstc";
                                reg = <0xf8048000 0x10>;
                                clocks = <&clk32k>;
index 8fa423c..2d0935a 100644 (file)
                                clock-names = "slow_clk", "main_xtal";
                        };
 
-                       reset_controller: rstc@fffffe00 {
+                       reset_controller: reset-controller@fffffe00 {
                                compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
                                reg = <0xfffffe00 0x10>;
                                clocks = <&clk32k>;
index 7b92426..1e5c018 100644 (file)
                                };
                        };
 
-                       reset_controller: rstc@fc068600 {
+                       reset_controller: reset-controller@fc068600 {
                                compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
                                reg = <0xfc068600 0x10>;
                                clocks = <&clk32k>;