drm/tilcdc: fix pixel clock setting warning message
authorDario Binacchi <dariobin@libero.it>
Mon, 22 Mar 2021 21:33:37 +0000 (22:33 +0100)
committerJyri Sarha <jyri.sarha@iki.fi>
Wed, 24 Mar 2021 10:05:28 +0000 (12:05 +0200)
The warning message did not printed the LCD pixel clock rate but the LCD
clock divisor input rate. As a consequence, the required and real pixel
clock rates are now passed to the tilcdc_pclk_diff().

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Jyri Sarha <jyri.sarha@iki.fi>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Jyri Sarha <jyri.sarha@iki.fi>
Link: https://patchwork.freedesktop.org/patch/msgid/20210322213337.26667-4-dariobin@libero.it
drivers/gpu/drm/tilcdc/tilcdc_crtc.c

index 25278f5..29890d7 100644 (file)
@@ -203,7 +203,7 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
        struct drm_device *dev = crtc->dev;
        struct tilcdc_drm_private *priv = dev->dev_private;
        struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
-       unsigned long clk_rate, real_rate, real_pclk_rate, pclk_rate;
+       unsigned long clk_rate, real_pclk_rate, pclk_rate;
        unsigned int clkdiv;
        int ret;
 
@@ -239,12 +239,12 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
                 * 5% is an arbitrary value - LCDs are usually quite tolerant
                 * about pixel clock rates.
                 */
-               real_rate = clkdiv * pclk_rate;
+               real_pclk_rate = clk_rate / clkdiv;
 
-               if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) {
+               if (tilcdc_pclk_diff(pclk_rate, real_pclk_rate) > 5) {
                        dev_warn(dev->dev,
-                                "effective pixel clock rate (%luHz) differs from the calculated rate (%luHz)\n",
-                                clk_rate, real_rate);
+                                "effective pixel clock rate (%luHz) differs from the requested rate (%luHz)\n",
+                                real_pclk_rate, pclk_rate);
                }
        }