if (of_machine_is_compatible("fsl,imx8mp") ||
of_machine_is_compatible("fsl,imx91") ||
of_machine_is_compatible("fsl,imx93")) {
- /* Binding doc describes the propety:
+ /* Binding doc describes the property:
* is required by i.MX8MP, i.MX91, i.MX93.
- * is optinoal for i.MX8DXL.
+ * is optional for i.MX8DXL.
*/
dwmac->intf_regmap =
syscon_regmap_lookup_by_phandle_args(np, "intf_mode", 1,
v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
- /* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
+ /* The timeout was previously set to 10ms, but some board (OrangePI0)
* need more if no cable plugged. 100ms seems OK
*/
err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
return ret;
}
- /* Make sure the EPHY is properly reseted, as U-Boot may leave
+ /* Make sure the EPHY is properly reset, as U-Boot may leave
* it at deasserted state, and thus it may fail to reset EMAC.
*
* This assumes the driver has exclusive access to the EPHY reset.
/*--- DMA BLOCK defines ---*/
/* DMA Bus Mode register defines */
-/* Programmable burst length (passed thorugh platform)*/
+/* Programmable burst length (passed through platform)*/
#define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */
#define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
memset(mc_filter, 0, sizeof(mc_filter));
netdev_for_each_mc_addr(ha, dev) {
/* The upper 6 bits of the calculated CRC are used to
- * index the contens of the hash table
+ * index the contents of the hash table
*/
int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
/* The most significant bit determines the register to
/* bits 5 7 0 | Frame status
* ----------------------------------------------------------
- * 0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)
+ * 0 0 0 | IEEE 802.3 Type frame (length < 1536 octets)
* 1 0 0 | IPv4/6 No CSUM errorS.
* 1 0 1 | IPv4/6 CSUM PAYLOAD error
* 1 1 0 | IPv4/6 CSUM IP HR error
writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK);
}
-/* This reads the MAC core counters (if actaully supported).
+/* This reads the MAC core counters (if actually supported).
* by default the MMC core is programmed to reset each
* counter after a read. So all the field of the mmc struct
* have to be incremented.
*dest = *dest + tmp;
}
-/* This reads the MAC core counters (if actaully supported).
+/* This reads the MAC core counters (if actually supported).
* by default the MMC core is programmed to reset each
* counter after a read. So all the field of the mmc struct
* have to be incremented.
unsigned long data;
u32 reg_value;
- /* For GMAC3.x, 4.x versions, in "fine adjustement mode" set sub-second
+ /* For GMAC3.x, 4.x versions, in "fine adjustment mode" set sub-second
* increment to twice the number of nanoseconds of a clock cycle.
* The calculation of the default_addend value by the caller will set it
* to mid-range = 2^31 when the remainder of this division is zero,
stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
STMMAC_DEFAULT_TWT_LS);
- /* Try to cnfigure the hardware timer. */
+ /* Try to configure the hardware timer. */
ret = stmmac_set_lpi_mode(priv, priv->hw, STMMAC_LPI_TIMER,
priv->tx_lpi_clk_stop, priv->tx_lpi_timer);
/**
* stmmac_mtl_configuration - Configure MTL
* @priv: driver private structure
- * Description: It is used for configurring MTL
+ * Description: It is used for configuring MTL
*/
static void stmmac_mtl_configuration(struct stmmac_priv *priv)
{
/* Always insert VLAN tag to SKB payload for TSO frames.
*
- * Never insert VLAN tag by HW, since segments splited by
+ * Never insert VLAN tag by HW, since segments split by
* TSO engine will be un-tagged by mistake.
*/
if (skb_vlan_tag_present(skb)) {
unsigned long flags;
spin_lock_irqsave(&ch->lock, flags);
- /* Both RX and TX work done are compelte,
+ /* Both RX and TX work done are complete,
* so enable both RX & TX IRQs.
*/
stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
/**
* stmmac_ioctl - Entry point for the Ioctl
* @dev: Device pointer.
- * @rq: An IOCTL specefic structure, that can contain a pointer to
+ * @rq: An IOCTL specific structure, that can contain a pointer to
* a proprietary structure used to pass information to the driver.
* @cmd: IOCTL command
* Description:
* If a specific clk_csr value is passed from the platform
* this means that the CSR Clock Range selection cannot be
* changed at run-time and it is fixed (as reported in the driver
- * documentation). Viceversa the driver will try to set the MDC
+ * documentation). Vice versa the driver will try to set the MDC
* clock dynamically according to the actual clock input.
*/
static u32 stmmac_clk_csr_set(struct stmmac_priv *priv)
}
/*
- * First tests will always be MAC / PHY loobpack. If any of
+ * First tests will always be MAC / PHY loopback. If any of
* them is not supported we abort earlier.
*/
if (ret) {
projects / linux-2.6-microblaze.git / commitdiff