phy: qcom-qmp: Use phy_status field for the status bit offset

In preparation of the support for v4.20 PCIe PHY in SDX55, use a
separate "phy_status" field for the status bit offset. This is needed
because, the v4.20 PHY uses a different offset for the PHY Status.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210427065400.18958-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index db12616..3623d5c 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -2525,6 +2525,8 @@ struct qmp_phy_cfg {
        unsigned int start_ctrl;
        unsigned int pwrdn_ctrl;
        unsigned int mask_com_pcs_ready;
+       /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
+       unsigned int phy_status;
 
        /* true, if PHY has a separate PHY_COM control block */
        bool has_phy_com_ctrl;
@@ -2738,6 +2740,7 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 };
 
 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
@@ -2763,6 +2766,7 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
        .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
        .mask_com_pcs_ready     = PCS_READY,
+       .phy_status             = PHYSTATUS,
 
        .has_phy_com_ctrl       = true,
        .has_lane_rst           = true,
@@ -2792,6 +2796,7 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = {
 
        .start_ctrl             = SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .no_pcs_sw_reset        = true,
 };
@@ -2818,6 +2823,7 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 };
 
 static const char * const ipq8074_pciephy_clk_l[] = {
@@ -2850,6 +2856,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
+       .phy_status             = PHYSTATUS,
 
        .has_phy_com_ctrl       = false,
        .has_lane_rst           = false,
@@ -2912,6 +2919,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
 
        .start_ctrl             = PCS_START | SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
+       .phy_status             = PHYSTATUS,
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = 995,          /* us */
@@ -2940,6 +2948,7 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
 
        .start_ctrl             = PCS_START | SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
+       .phy_status             = PHYSTATUS,
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = 995,          /* us */
@@ -2978,6 +2987,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
 
        .start_ctrl             = PCS_START | SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
+       .phy_status             = PHYSTATUS,
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = 995,          /* us */
@@ -3016,6 +3026,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
 
        .start_ctrl             = PCS_START | SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
+       .phy_status             = PHYSTATUS,
 
        .is_dual_lane_phy       = true,
        .has_pwrdn_delay        = true,
@@ -3045,6 +3056,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
@@ -3076,6 +3088,7 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
@@ -3147,6 +3160,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
@@ -3173,6 +3187,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
 
        .start_ctrl             = SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .is_dual_lane_phy       = true,
        .no_pcs_sw_reset        = true,
@@ -3200,6 +3215,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
+       .phy_status             = PHYSTATUS,
 };
 
 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
@@ -3224,6 +3240,7 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .is_dual_lane_phy       = true,
 };
@@ -3248,6 +3265,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
 
        .start_ctrl             = SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .is_dual_lane_phy       = true,
 };
@@ -3274,6 +3292,8 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
+
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
@@ -3305,6 +3325,7 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
@@ -3333,6 +3354,7 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
@@ -3364,6 +3386,7 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
@@ -3432,6 +3455,7 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
@@ -3458,6 +3482,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
 
        .start_ctrl             = SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .is_dual_lane_phy       = true,
 };
@@ -3484,6 +3509,7 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
@@ -3515,6 +3541,7 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
 
        .start_ctrl             = SERDES_START | PCS_START,
        .pwrdn_ctrl             = SW_PWRDN,
+       .phy_status             = PHYSTATUS,
 
        .has_pwrdn_delay        = true,
        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
@@ -4382,7 +4409,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
                        ready = PCS_READY;
                } else {
                        status = pcs + cfg->regs[QPHY_PCS_STATUS];
-                       mask = PHYSTATUS;
+                       mask = cfg->phy_status;
                        ready = 0;
                }